EE Distinguished Speakers Seminar Series: Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs

Abstract
In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, III-V compound semiconductors have received a great deal of attention as possible alternatives. Sub-10 nm CMOS require high-aspect ratio 3D transistors with a fin or nanowire geometry. The enhanced degree of channel charge control of advanced 3D designs allows for transistor size scaling to extremely small dimensions. At MIT, we are investigating the prospects of nanoscale InGaAs FinFETs and vertical nanowire (VNW) MOSFETs fabricated through a top-down approach. We have demonstrated devices with sub-10 nm critical dimensions and record electrical characteristics. More recently, we have developed thermal atomic-layer etching (TALE) for InGaAs and InAlAs. We have shown that in-situ integration of TALE with atomic layer deposition of the gate dielectric allows the fabrication of the gate stack without exposure to air. This has yielded the most scaled InGaAs FinFETs to date with sub-3 nm fin widths and record ON-and OFF-state characteristics. Our studies reveal OFF-state leakage current, mobility degradation and gate oxide trapping as major stumbling blocks for future use of InGaAs 3D transistors in logic applications. This talk will review these and other problematic issues with III-V CMOS and discuss possible solutions.