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SUMMARY:IEM Distinguished Lecturer Seminar: Accelerator Architectures for 
 Deep Neural Networks: Inference and Training
DTSTART:20211129T141500
DTEND:20211129T151500
DTSTAMP:20260602T023156Z
UID:f2d9bbcf4293ccf877fe53462da26ad1c15931027405c61defc01b7b
CATEGORIES:Conferences - Seminars
DESCRIPTION:Keshab K. Parhi\, Dept. of Electrical & Computer Engineering U
 niversity of Minnesota\, Minneapolis\, http://people.ece.umn.edu/~parhi\nA
 bstract:\nMachine learning and data analytics continue to expand the fourt
 h industrial revolution and affect many aspects of our lives. The talk wil
 l explore hardware accelerator architectures for deep neural networks (DNN
 s). I will present a brief review of history of neural networks (OJCAS-202
 0). I will talk about our recent work on Perm-DNN based on permuted-diagon
 al interconnections in deep convolutional neural networks and how structur
 ed sparsity can reduce energy consumption associated with memory access in
  these systems (MICRO-2018). I will then talk about reducing latency and m
 emory access in accelerator architectures for training DNNs by gradient in
 terleaving using systolic arrays (ISCAS-2020). Then I will present our rec
 ent work on LayerPipe\, an approach for training deep neural networks that
  leads to simultaneous intra-layer and inter-layer pipelining (ICCAD-2021)
 . This approach can increase processor utilization efficiency and increase
  speed of training without increasing communication costs.\n\nBio:\nKeshab
  K. Parhi received the B.Tech. degree from the Indian Institute of Technol
 ogy (IIT)\, Kharagpur\, in 1982\, the M.S.E.E. degree from the University 
 of Pennsylvania\, Philadelphia\, in 1984\, and the Ph.D. degree from the U
 niversity of California\, Berkeley\, in 1988. He has been with the Univers
 ity of Minnesota\, Minneapolis\, since 1988\, where he is currently Distin
 guished McKnight University Professor and Edgar F. Johnson Professor of El
 ectronic Communication in the Department of Electrical and Computer Engine
 ering. He has published over 650 papers\, is the inventor of 32 patents\, 
 and has authored the textbook VLSI Digital Signal Processing Systems (Wile
 y\, 1999) and coedited the reference book Digital Signal Processing for Mu
 ltimedia Systems (Marcel Dekker\, 1999). His current research addresses VL
 SI architecture design of machine learning systems\, hardware security\, d
 ata-driven neuroscience and molecular/DNA computing. Dr. Parhi is the reci
 pient of numerous awards including the 2017 Mac Van Valkenburg award and t
 he 2012 Charles A. Desoer Technical Achievement award from the IEEE Circui
 ts and Systems Society\, the 2004 F. E. Terman award from the American Soc
 iety of Engineering Education\, and the 2003 IEEE Kiyo Tomiyasu Technical 
 Field Award. He served as the Editor-in-Chief of the IEEE Trans. Circuits 
 and Systems\, Part-I during 2004 and 2005. He is a Fellow of IEEE\, ACM\, 
 AAAS and the National Academy of Inventors.\n 
LOCATION:BM 5202 https://plan.epfl.ch/?room==BM%205202 https://epfl.zoom.u
 s/j/64183611534
STATUS:CONFIRMED
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