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PRODID:-//Memento EPFL//
BEGIN:VEVENT
SUMMARY:Logic Synthesis for High-Performance Hardware
DTSTART:20220616T110000
DTEND:20220616T130000
DTSTAMP:20260408T020609Z
UID:3238620a360be02e6df1db6fec4ed20b72c0deb9958c2d05d032cc9c
CATEGORIES:Conferences - Seminars
DESCRIPTION:Andrea Costamagna\nEDIC candidacy exam\nExam president: Prof. 
 Andreas Burg\nThesis advisor: Prof. Giovanni de Micheli\nCo-examiner: Prof
 . Paolo Ienne\n\nAbstract\nLogic synthesis is a design phase that optimize
 s abstract circuit representations and maps them to technology. Combined w
 ith Dennard scaling\, this field of research has been the driving force be
 hind the Digital Revolution\, enabling the design of very large-scale inte
 grated circuits. With CMOS devices at the nanometer range\, scaling transi
 stors down can no longer guarantee a financially and energetically sustain
 able exponential growth in computing power. Hence\, the paramount need for
  speed improvements requires the development of more efficient synthesis p
 aradigms. Technology-aware logic synthesis is a recent trend in the indust
 ry targeting the introduction of technological information early in the de
 sign flow. This approach yields improved Quality of Results\, induced by a
  better correlation between RTL synthesis and physical implementation. A r
 ecent breakthrough in technology-aware delay synthesis enabled the optimiz
 ation of circuit designs up to local optimality [1]. Further advancements 
 in the field require extending optimality toward less-local circuit portio
 ns. The proposed approach for achieving this goal involves combining the r
 esults in two branches of research. On the one hand\, there are technology
 -oriented synthesis heuristics. The presented symmetry-detection-based syn
 thesis technique is an example [2]. On the other hand\, there are flexible
  data structures for Boolean reasoning [3]. This proposal reviews the ment
 ioned background [1]-[3] and discusses a strategy to advance the research 
 toward higher-performance hardware.\n\nBackground papers\n\n	 Mishchenko\
 , Alan\, et al. "FRAIGs: A unifying representation for logic synthesis and
  verification". ERL Technical Report\, 2005. https://ptolemy.berkeley.edu/
 projects/embedded/mvsis/doc/2004/fraigs.pdf\n	Amarú\, Luca\, et al. "Enab
 ling exact delay synthesis." 2017 IEEE/ACM International Conference on Com
 puter-Aided Design (ICCAD). IEEE\, 2017. https://ieeexplore.ieee.org/abstr
 act/document/8203799\n	Edwards\, C. R.\, & Hurst\, S. L. (1978). "A digita
 l synthesis procedure under function symmetries and mapping methods". IEEE
  Transactions on Computers\, 27(11)\, 985-997. https://ieeexplore.ieee.org
 /abstract/document/1674988\n
LOCATION:INF 328 https://plan.epfl.ch/?room==INF%20328
STATUS:CONFIRMED
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