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SUMMARY:Machine Learning for FPGA Computer-Aided Design
DTSTART:20220616T093000
DTEND:20220616T113000
DTSTAMP:20260501T182140Z
UID:700834848756adbef22fe800a4612eef2f16019b34218a76216a908c
CATEGORIES:Conferences - Seminars
DESCRIPTION:Shashwat Shrivastava\nEDIC candidacy exam\nExam president: Pro
 f. Giovani De Micheli\nThesis advisor: Prof. Babak Falsafi\nThesis co-advi
 sior: Dr. Mirjana Stojilovic\nCo-examiner: Prof. Patrick Thiran\n\nAbstra
 ct\nFPGAs have proven to be an efficient platform for applications in the 
 domain of video and image processing\, machine learning\, genomics\, wirel
 ess communication\, scientific computations\, and medical. The diversity o
 f domains targeted by FPGAs accounts from the fact that they offer reprogr
 ammability\, low-power consumption\, fine-grained parallelism\, and short 
 design time as compared to ASICs. However\, the term 'short design time' i
 s often misleading. With technology scaling\, the design time of FPGA desi
 gns varies from hours to days. Moreover\, the same design flow is repeated
  multiple times to achieve satisfactory hardware implementation.\n \nFPGA
  CAD flow (or compilation flow) comprises four main stages\, out of which\
 , placement and routing take up the maximum amount of time. The traditiona
 l approaches produce satisfactory sub-optimal results (given NP-completene
 ss of problems)\, however\, have long runtimes. Researchers have tried to 
 integrate some Machine Learning techniques in the FPGA CAD flow to speed-u
 p placement. However\, little has been done to accelerate the routing proc
 ess while maintaining the high Quality of Results (QoR). In my thesis\, I 
 would like to develop an ML-driven routing algorithm that achieves high Qo
 R at high speed.\n\nBackground papers\nPaper 1. PathFinder: A Negotiation-
 based Performance-driven Router for FPGAs (Listed in 25 most influential 
 papers for FPGAs)\nPaper 2. Machine-Learning Based Congestion Estimation f
 or Modern FPGAs (Best paper award FPL'2018)\nPaper 3. GPlace3.0: Routabil
 ity-Driven Analytic Placer for UltraScale FPGA Architectures\n\n 
LOCATION:BC 010 https://plan.epfl.ch/?room==BC%20010
STATUS:CONFIRMED
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