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SUMMARY:Elastic Coarse Grained Reconfigurable Array
DTSTART:20220629T100000
DTEND:20220629T120000
DTSTAMP:20260407T141546Z
UID:257e385f45f8792329c680209b977c8106c5f52f48bdab84323cb67f
CATEGORIES:Conferences - Seminars
DESCRIPTION:Louis Coulon\nEDIC candidacy exam\nExam president: Prof. Marti
 n Odersky\nThesis advisor: Prof. Paolo Ienne\nThesis co-advisor: Dr. Mirja
 na Stojilovic\nCo-examiner: Prof. Babak Falsafi\n\nAbstract\nWith the end 
 of Moore's law and Dennard scaling\, there is an increasing need for hardw
 are specialization to meet the computational requirements of applications 
 and run them with improved energy efficiency. Programmable devices\, such 
 as Field Programmable Gate Arrays (FPGAs)\, are good candidates to meet su
 ch needs as they allow designers to customize the hardware for each applic
 ation. While programming FPGAs using Hardware Description Languages such a
 s VHDL or Verilog allows one to achieve efficient implementations\, it req
 uires in-depth hardware knowledge and limits the utilization of FPGAs. As 
 a result\, to widen the adoption of FPGAs\, other programming paradigms su
 ch as High-Level Synthesis(HLS)\, which compiles high-level programs to ci
 rcuits\, have been developed. However\, HLS-generated circuits might lead 
 to\, surprisingly\, moderately efficient implementations. Indeed\, FPGAs a
 re bit-level devices based on LUTs\, while programs are usually word-level
 \, making them a poor fit for such an architecture. Another type of archit
 ectures\, Coarse Grained Reconfigurable Arrays (CGRAs)\, could be more sui
 table but are also a poor fit since they are generally small and only supp
 ort flavors of modulo scheduling. This poor fit calls for another type of 
 architecture. During the presentation\, we will first go over recent work 
 on dynamically scheduled high-level synthesis\, which brings out-of-order 
 execution to circuits. Then\, we will review some of the main design direc
 tions followed so far in CGRA architecture. Finally\, we will underline th
 e missing pieces of current CGRA designs and the future work directions we
  are investigating.\n\nBackground papers\n[1] https://ieeexplore.ieee.org/
 document/9439439\n\n[2] https://ieeexplore.ieee.org/document/1611540\n\n[3
 ] https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1188678\n 
LOCATION:BC 233 https://plan.epfl.ch/?room==BC%20233
STATUS:CONFIRMED
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