BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Memento EPFL//
BEGIN:VEVENT
SUMMARY:IEM Distinguished Lecturers Seminar: Energy Efficient Circuits Bey
 ond what have been believed as the Fundamental Limits: Power Converter\, A
 nalog Interface and Frequency Generation
DTSTART:20230414T131500
DTEND:20230414T140000
DTSTAMP:20260920T193058Z
UID:f3e1b5a2f312cb13ab089d86bee7cbd973c3d613492101cf2eaf1113
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Taekwang Jang\, \nDept. of Information Technology and El
 ectrical Engineering\, ETH Zürich\nThe seminar will take place in ELA 2 a
 nd will be simultaneously broadcasted in the main auditorium in Neuchâte
 l Campus (MC A1 272).\n\nCoffee and cookies will be served at 13:00 befor
 e the seminar\, in front of the two auditoriums. \n\nAbstract\nAs circuit
  designers\, we are entering an exciting new era where innovations in circ
 uits are the key enablers for reshaping the future. With the emerging tren
 ds in Machine Learning\, Internet-of-Everything\, Brain-Machine Interfaces
 \, Autonomous Driving\, 6G Communication\, Quantum Computing\, and many mo
 re cutting-edge technologies\, circuit designers are required to make dras
 tic improvements in accuracy\, speed\, and energy efficiency.\n\nYet\, as 
 the CMOS circuit theories and design methodologies have been optimized and
  matured over the past five decades\, we often encounter what so believed 
 as the fundamental limit that confines the maximum achievable performance 
 of a circuit. This may lead us to believe that no meaningful improvements 
 can be made to it. However\, such a limit is sometimes restricted to a spe
 cific topology or methodology\, i.e.\, not so fundamental\, the circuit ma
 y still have the potential to improve even by order of magnitude. As examp
 les\, I will explain our recent designs of 1) an on-chip high-power-densit
 y DC-DC converter 2) a noise-efficient sensor interface\, and 3) a wide-ba
 ndwidth phase-locked loop that exceed previously believed limitations.\n\n
 Bio\nTaekwang Jang (S’06-M’13-SM’19) received his B.S. and M.S. in e
 lectrical engineering from KAIST\, Korea\, in 2006 and 2008\, respectively
 . From 2008 to 2013\, he worked at Samsung Electronics\, focusing on mixed
 -signal circuit design\, including analog and all-digital PLLs. In 2017\, 
 he received his Ph.D. from the University of Michigan\; his dissertation w
 as titled “Circuit and System Designs for Millimeter-Scale IoT and Wirel
 ess Neural Recording.” After working as a post-doctoral research fellow\
 , he joined the ETH Zürich in 2018 as an assistant professor and is leadi
 ng the Energy-Efficient Circuits and IoT Systems group. He is also a membe
 r of the Competence Center for Rehabilitation Engineering and Science\, an
 d the chair of IEEE solid-state circuits society\, Switzerland chapter.\n\
 nHis research focuses on circuits and systems for highly energy-constraine
 d applications such as wireless sensor nodes and biomedical interfaces. Es
 sential building blocks such as a sensor interface\, energy harvester\, po
 wer converter\, communication transceiver\, frequency synthesizer\, and da
 ta converters are his primary interests. He holds 14 patents and has (co)a
 uthored more than 60 peer-reviewed conferences and journal articles. He is
  the recipient of the IEEE ISSCC 2021 and 2022 Jan Van Vessem Award for Ou
 tstanding European Paper\, the IEEE ISSCC 2022 Outstanding Forum Speaker A
 ward\, and the 2009 IEEE CAS Guillemin-Cauer Best Paper Award. Since 2022\
 , he has been a TPC member of the IEEE International Solid-State Circuits 
 Conference (ISSCC)\, IMMD Subcommittee\, and IEEE Asian Solid-State Circui
 ts Conference (ASSCC)\, Analog Subcommittee. He is also an associate edito
 r for the Journal of Solid-State Circuits (JSSC).\n 
LOCATION:ELA 2 https://plan.epfl.ch/?room==ELA%202 https://epfl.zoom.us/j/
 63596420243
STATUS:CONFIRMED
END:VEVENT
END:VCALENDAR