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SUMMARY:IEM Seminar Series: In-memory Computing – Fundamentals\, Current
  Trends\, and Future Directions
DTSTART:20230324T111500
DTEND:20230324T120000
DTSTAMP:20260407T024824Z
UID:ca02ce30cbec20fa5d29fc8708825ca4e8c9684ea5a360ffbaad9bd8
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Naresh R. Shanbhag\,\nJack Kilby Professor of Electrical
  and Computer Engineering\nUniversity of Illinois\, Urbana-Champaign\, US\
 nAbstract\nIn-memory computing (IMC) has emerged as an attractive compleme
 nt to digital accelerators for enhancing the energy efficiency of machine 
 learning tasks. IMC addresses the energy and latency costs of memory acces
 ses dominating AI workloads by transforming the conventional memory access
 es into one that computes functions of data in the memory core in an analo
 g/mixed-signal manner. As a result\, IMC chips have demonstrated > 100X re
 duction in the energy-delay product over equivalent von Neumann architectu
 res at iso-accuracy. IMCs also exhibit a fundamental energy vs. SNR trade-
 off that designers need to exploit to enhance energy efficiency while meet
 ing task-level accuracy requirements. Since the publication of the concept
  in our ICASSP 2014 paper\, IMC design has become an active area of resea
 rch in the machine learning integrated circuits and architecture communiti
 es. This talk will describe IMC design principles\, review current trends 
 based on our recent efforts in extensive benchmarking (https://github.com/
 naresh-shanbhag/UIUC-IMC-Benchmarking)\, and identify future opportunities
  and challenges in deploying IMCs at scale in emerging applications.\n\nBi
 o\nNaresh R. Shanbhag is the Jack Kilby Professor of Electrical and Comput
 er Engineering at the University of Illinois at Urbana-Champaign. He recei
 ved his Ph.D. degree from the University of Minnesota (1993) in Electrical
  Engineering. From 1993 to 1995\, he worked at AT&T Bell Laboratories at M
 urray Hill where he led the design of high-speed transceiver chipsets for 
 very high-speed digital subscriber line (VDSL)\, before joining the Univer
 sity of Illinois at Urbana- Champaign in August 1995. He has held visiting
  faculty appointments at the National Taiwan University (Aug.-Dec. 2007) a
 nd Stanford University (Aug.-Dec. 2014). His research focuses on the desig
 n of energy-efficient systems for machine learning\, communications\, and 
 signal processing\, spanning algorithms\, VLSI architectures\, and integra
 ted circuits. He has more than 200 publications in this area\, holds thirt
 een US patents\, and is a co-author of two books and multiple book chapter
 s (see https://shanbhag.ece.illinois.edu/ for details).\nDr. Shanbhag rece
 ived the 2018 SIA/SRC University Researcher Award\, became an IEEE Fellow 
 in 2006\, received the 2010 Richard Newton GSRC Industrial Impact Award\, 
 the IEEE Circuits and Systems Society Distinguished Lecturership in 1997\,
  the National Science Foundation CAREER Award in 1996\, and multiple best 
 paper awards. In 2000\, Dr. Shanbhag co-founded and served as the Chief Te
 chnology Officer of the Intersymbol Communications\, Inc.\, which introduc
 ed mixed-signal ICs for electronic dispersion compensation of OC-192 optic
 al links\, and became a part of Finisar Corporation in 2007. From 2013-17\
 , he was the founding Director of the Systems On Nanoscale Information fab
 riCs (SONIC) Center\, a 5-year multi- university center funded by DARPA an
 d SRC under the STARnet program. He is currently on the leadership teams o
 f the JUMP 2.0 DARPA and SRC funded Centers for Ubiquitous Connectivity (C
 UbiC) and Codesign of Cognitive Systems (CoCoSys)\, and the NSF-industry f
 unded Center for Advanced Semiconductor Chips for Accelerated Performance 
 (ASAP).
LOCATION:INF 328 https://plan.epfl.ch/?room==INF%20328 https://epfl.zoom.u
 s/j/62666328156
STATUS:CONFIRMED
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