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SUMMARY:Dynamic Acceleration of Task-Parallel Algorithms on FPGAs
DTSTART:20230602T093000
DTEND:20230602T113000
DTSTAMP:20260407T061624Z
UID:86b1cbed8080e6c9264f27e9f6e780ff5062e77a5bb78f3b0d9a78be
CATEGORIES:Conferences - Seminars
DESCRIPTION:Mohamed Mahfouz Ahmed Kotb Shahawy\nEDIC candidacy exam\nExam 
 president: Prof. Edouard Bugnion\nThesis advisor: Prof. Paolo Ienne\nCo-ex
 aminer: Prof. Rachid Guerraoui\n\nAbstract\nField Programmable Gate Arrays
  (FPGAs) witnessed multiple leaps in their programmability through the dev
 elopment of High-Level Synthesis (HLS) tools that enabled more accessibili
 ty to non-expert users of FPGAs. The current HLS tools exploit specific ty
 pes of parallelism in the produced circuits\, like Instruction Level Paral
 lelism  (ILP). Support of Task-Level Parallelism (TLP) in HLS has been re
 cently explored on FPGAs with systems like ParallelXL\, TAPAS\, and TaPaSC
 o. This report examines TLP from a software side through the Cilk runtime 
 system. Second\, it analyzes ParallelXL\, an effort to bring TLP support t
 o FPGAs using the programming model from Cilk. Then\, it investigates a re
 cent graph cycle enumeration algorithm that uses software TLP as a possibl
 e candidate for FPGA acceleration. Finally\, the report concludes with a r
 esearch proposal that identifies the line of research to support TLP for F
 PGAs.\n\nBackground papers\n\n	An Architectural Framework for Accelerating
  Dynamic Parallel Algorithms on Reconfigurable Hardware (https://ieeexplor
 e.ieee.org/document/8574531)\n	Cilk: an efficient multithreaded runtime sy
 stem (https://dl.acm.org/doi/10.1145/209937.209958)\n	Scalable Fine-Graine
 d Parallel Cycle Enumeration Algorithms (https://dl.acm.org/doi/10.1145/34
 90148.3538585)\n
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STATUS:CONFIRMED
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