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SUMMARY:IC Talk: Programmable Hardware (FPGAs) for Efficient Deep Learning
  Inference and Reinforcement Learning for Efficient FPGA CAD
DTSTART:20230616T101500
DTEND:20230616T111500
DTSTAMP:20260407T182205Z
UID:13c7e5e81ed5440368eb7ac8147fffb1ef2ecba9457c076e28fad73c
CATEGORIES:Conferences - Seminars
DESCRIPTION:Vaughn Betz - University of Toronto\n\n\n\nAbstract: The first
  part of this talk discusses what FPGAs can do for deep learning. FPGAs ar
 e computer chips in which both the logic functions and the  connectivity 
 between them can be reprogrammed\, enabling custom processing pipelines wh
 ere the numeric precision\, memory layout and more can adapt to best match
  a deep learning (DL) algorithm and where the programmable I/O can enable 
 unique embedded systems. We discuss the strengths and weaknesses of FPGAs 
 in the DL domain\, styles of DL accelerators that can be programmed into F
 PGAs to yield power-efficient and low-latency DL  acceleration\, and some
  future research areas to enhance efficiency further.\n\nThe second part o
 f this talk focuses on what reinforcement learning can do for FPGAs. The l
 ow-level programmability of FPGAs necessitates a complex computer-aided de
 sign (CAD) flow to translate a high-level specification by a hardware engi
 neer into the millions of programming bits that configure the chip.  The 
 most time-consuming part of this CAD flow is typically placement\, which c
 hooses where each one of hundreds of thousands or millions of hardware pri
 mitives should be located within the FPGA. We will discuss how reinforceme
 nt learning can be combined with the simulated annealing meta-heuristic to
  find quality-enhancing perturbations of a placement\, reducing the CPU ti
 me needed to obtain an acceptable solution by over 2X.\n\n\nBio:  Vaughn 
 Betz is a Professor at the University of Toronto in the Department of Elec
 trical and Computer Engineering\, and a Faculty Affiliate of the Vector  
 Institute for Artificial Intelligence. He is the original developer of the
  widely used VPR FPGA placement\, routing and architecture evaluation CAD 
 flow\, and a  lead developer in the VTR project that has built upon VPR. 
 He co-founded Right Track CAD to develop new FPGA CAD tools and architectu
 res\, and joined  Altera upon Right Track CAD’s acquisition. Dr. Betz s
 pent 11 years at Altera (now part of Intel)\, ultimately as Senior Directo
 r of software engineering\, and is  one of the architects of the Quartus 
 CAD system and the first five generations of the Stratix and Cyclone FPGA 
 families. He holds 102 US patents and has  published over 150 technical a
 rticles in the FPGA area\, fifteen of which have won best or most signific
 ant paper awards. Dr. Betz is a Fellow of the IEEE\, the  National Academ
 y of Inventors and the Engineering Institute of Canada.\n\n\n
LOCATION:BC 02 https://plan.epfl.ch/?room==BC%2002
STATUS:CONFIRMED
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