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SUMMARY:Processor Microarchitectural Optimizations for Performance Density
DTSTART:20230726T130000
DTEND:20230726T150000
DTSTAMP:20260428T211155Z
UID:f1f5d00d611c8a9896861b15befcb6a03cdd67dd3db9fe1cf136c0e1
CATEGORIES:Conferences - Seminars
DESCRIPTION:Bugra Eryilmaz\nEDIC candidacy exam\nExam president: Prof. Tho
 mas Bourgeat\nThesis advisor: Prof. Babak Falsafi\nCo-examiner: Prof. Davi
 d Ateinza\n\nAbstract\nAs we reach the end of Moore's Law and Dennard Scal
 ing\, we cannot rely on transistor scaling to improve the performance and 
 efficiency of processors. Instead\, we need to rely on architectural and m
 icroarchitectural design techniques to improve the performance and efficie
 ncy of processors. In the server workloads\, the performance density\, i.e
 . performance per unit silicon area\, is one of the most important metrics
  to achieve higher total performance with a given area for server processo
 rs. The research proposal focuses on architectural and microarchitectural 
 design techniques such as cache coherence\, Out-of-Order (OoO) execution\,
  and Simultaneous Multithreading (SMT) to improve the performance density 
 of server processors.\n\nBackground papers\n1) Scale-Out Processors [ISCA1
 2'] https://dl.acm.org/doi/10.1145/2366231.2337217 Pejman Lotfi-Kamran\, B
 oris Grot\, Michael Ferdman\, Stavros Volos\, Onur Kocberber\, Javier Pico
 rel\, Almutaz Adileh\, Djordje Jevdjic\, Sachin Idgunji\, Emre Ozer\, and 
 Babak Falsafi.\n2) MorphCore: An Energy-Efficient Microarchitecture for Hi
 gh Performance ILP and High Throughput TLP [MICRO12'] https://ieeexplore.i
 eee.org/document/6493629 Khubaib\, M. A. Suleman\, M. Hashemi\, C. Wilkers
 on and Y. N. Patt\n3) Mirage cores: the illusion of many out-of-order core
 s using in-order hardware [MICRO17'] https://ieeexplore.ieee.org/document/
 8686674 S. Padmanabha\, A. Lukefahr\, R. Das and S. Mahlke
LOCATION:BC 129 https://plan.epfl.ch/?room==BC%20129
STATUS:CONFIRMED
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