BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Memento EPFL//
BEGIN:VEVENT
SUMMARY:Building Chips Faster: Hardware-Compiler Co-Design for Accelerated
  RTL Simulation
DTSTART:20230906T170000
DTSTAMP:20260414T233858Z
UID:84f2f238524df06ae2fd295306d1aaefb27b450d7990ef15e0628a19
CATEGORIES:Thesis defenses
DESCRIPTION:Sahand KASHANI-AKHAVAN\nThesis Director: Prof. J. R. Larus\,\n
 Computer and Communication Sciences doctoral program\nThesis Nr. 8990\n\n
 To take part in the public defense\, please contact directly the speaker
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420 https://epfl.zoom.us/
 j/3548647835?pwd=RU9qb3VKbElBcEc2VE9FclhkY25mZz09
STATUS:CONFIRMED
END:VEVENT
END:VCALENDAR