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SUMMARY:Performance Interface for Hardware Accelerators
DTSTART:20230907T093000
DTEND:20230907T113000
DTSTAMP:20260406T171954Z
UID:ed78d35046d8fecf65debbd44f8be43f08d7d70710287b394813cc7d
CATEGORIES:Conferences - Seminars
DESCRIPTION:Jiacheng Ma\nEDIC candidacy exam\nExam president: Prof. Babak 
 Falsafi\nThesis advisor: Prof. George Candea\nCo-examiner: Prof. Thomas Bo
 urgeat\n\nAbstract\nPropose performance interface for hardware circuit (RT
 L level) and querying latency or verifying performance properties through 
 proposed performance interface.\nHardware accelerators should come with pe
 rformance interfaces—interfaces that provide usable information about
  the accelerator’s performance behavior just like semantic interfaces
  do for functionality. Since accelerators aimed at improving system perfor
 mance\, their performance behavior should be clearly stated to the users\,
  through a performance interface.\nA performance interface intends to abst
 ract away implementation details that do not pertain to performance. A per
 formance interface should be systematically derived that leverage common c
 onstructs\, such that further tools can be invented to\nanalyze performanc
 e and verify performance properties of the hardware circuit automatically 
 through performance interface.  \n\nBackground papers\n\n	A Systematic A
 pproach to Achieving Tight Worst-Case Latency and High-Performance Under
  Predictable Cache Coherence (RTAS’2021)\n	Timeloop: A systematic appr
 oach to DNN accelerator Evaluation(ISPASS\, 2019)\n	Modeling and verificat
 ion of time dependent systems using time Petri nets (TSE\, 1991)\n
LOCATION:BC 233 https://plan.epfl.ch/?room==BC%20233
STATUS:CONFIRMED
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