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SUMMARY:IEM Distinguished Lecturers Seminar: Making Every Chip Hardware-Se
 cure and Physically-Patchable  – From Physical Design to On-Chip Machine
  Learning
DTSTART:20250117T100000
DTEND:20250117T110000
DTSTAMP:20260510T042345Z
UID:da30ea9b549b44c223a39c70b124b48e0d5e182ae3fe2eeed258ee1a
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Massimo Alioto\, \nECE - National University of Singapor
 e\n***Coffee and cookies will be served at 9h45 in the hall of BM 5202***\
 n\nAbstract\nIn next-generation secure silicon chips\, divide-and-conquer 
 design methodologies facilitate building block design but conflict with ba
 sic hardware security requirements. Also\, they preclude opportunities for
  efficient system integration and inexpensive embedment of security featur
 es. At the same time\, the insertion of security primitives as standalone 
 blocks is inherently additive in terms of area\, power\, design effort and
  integration effort\, limiting their embeddability in low-cost devices (i.
 e.\, the vast majority of the upcoming trillion chips for the Internet of 
 Things). As further limitation of conventional approaches to security enfo
 rcement in silicon chips (e.g.\, against side-channel attacks)\, the disco
 very of hardware vulnerabilities cannot be followed by later hardware fixe
 s as we are used to do with software systems.\nIn this keynote\, the road 
 towards ubiquitous hardware security is pursued from a primitive design pe
 rspective\, designing PUFs and TRNGs that are inherently immersed in exist
 ing memory arrays and logic fabrics\, and breaking the boundaries of tradi
 tional system partitioning. The new concept of hardware patching is also d
 iscussed\, where circuit flexibility is introduced to make silicon chips a
 ble to evolve over time and counteract newly discovered vulnerabilities th
 rough learning-based physical protection mechanisms.\n\nBio\nMassimo Aliot
 o is a Professor at the ECE Department of the National University of Singa
 pore\, where he leads the Green IC group\, the Integrated Circuits and Emb
 edded Systems area\, and the FD-fAbrICS center on intelligent&connected sy
 stems. Previously\, he held positions at the University of Siena\, Intel L
 abs – CRL (2013)\, University of Michigan - Ann Arbor (2011-2012)\, Univ
 ersity of California – Berkeley (2009-2011)\, EPFL - Lausanne.\nHe is (c
 o)author of 400 publications on journals and conference proceedings\, and 
 four books with Springer (with two more coming this quarter). His primary 
 research interests include ultra-low power and self-powered systems\, gree
 n computing\, circuits for machine intelligence\, hardware security\, and 
 emerging technologies.\nHe was the Editor in Chief of the IEEE Transaction
 s on VLSI Systems and Deputy Editor in Chief of the IEEE Journal on Emergi
 ng and Selected Topics in Circuits and Systems. He is/was the Chair of the
  Distinguished Lecturer Program for the IEEE CAS Society\, and Distinguish
 ed Lecturer for the SSC and CAS Society. Previously\, Prof. Alioto was the
  Chair of the “VLSI Systems and Applications” Technical Committee of t
 he IEEE Circuits and Systems Society (2010-2012). He served as Guest Edito
 r of numerous journal special issues (JSSC\, TCAS-I\, JETCAS…)\, Technic
 al Program Chair of several IEEE conferences (ISCAS\, SOCC\, PRIME\, ICECS
 )\, and TPC member (ISSCC\, ASSCC). His research group contribution has be
 en recognized through various best paper awards (e.g.\, ISSCC\, ICECS)\, a
 nd in the ten technological highlights of the TSMC 2020 annual report\, am
 ong the others. Prof. Alioto is an IEEE Fellow.
LOCATION:BM 5202 https://plan.epfl.ch/?room==BM%205202 https://epfl.zoom.u
 s/j/66352847538
STATUS:CONFIRMED
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