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SUMMARY:Leveraging FPGA Reconfigurability during Post-Silicon Debug and Va
 lidation: Opportunities\, Successes\, and Challenges
DTSTART:20130611T111500
DTEND:20130611T121500
DTSTAMP:20260510T022754Z
UID:ba274064a89a7969e5fc58e82dd449c239f14cc76286428a7c274330
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Steve Wilton\, University of British Columbia\nElectroni
 c devices have come to permeate every aspect of our daily lives.  At the 
 heart of these devices are Integrated Circuits.   State-of-the-art chips
  can now contain several billion transistors\; designing and verifying tha
 t these circuits function correctly under all expected (and unexpected) op
 eration conditions is extremely challenging.   While simulation is an im
 portant tool\, it is not sufficient\; simulation is slow\, and it is incre
 asingly important to be able to debug circuits in-situ.  Debugging fabric
 ated chips\, post-silicon\, is the only solution to ensure working systems
 .\nAn emerging tool in improving the debug experience is the use of Field-
 Programmable Gate Array (FPGA) technology.  In this talk\, we will focus 
 on two ways FPGA-like technology can be used to accelerate post-silicon de
 bug.  First\, we will show how debug productivity can be enhanced by embe
 dding small reconfigurable logic analyzers on chip\, and using these to no
 t only record traces\, but intelligently process data to control the syste
 m and make better use of existing on-chip trace storage.  Challenges incl
 ude minimizing the overhead while providing enough flexibility to support 
 many debug scenarios.\nSecond\, we will discuss how the reconfigurable nat
 ure of FPGAs can be used to efficiently provide observability while debugg
 ing in an FPGA prototyping environment.   In particular\, we will show h
 ow we can create flexible overlay networks that provide connectivity betwe
 en trace buffers and the circuit under test using unused FPGA routing reso
 urces.   We will show that this technique effectively results in no area
  and speed overhead to the circuit under test\, yet provides a significant
 ly improved debug experience.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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