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SUMMARY:Less is More: Experiences in Deconstructing Hardware Coherence
DTSTART:20130607T100000
DTEND:20130607T110000
DTSTAMP:20260408T003942Z
UID:1b3b65d70abc87242398533928664b48e3d6d87ec2b30cfb5bea1755
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Stefanos Kaxiras\, Uppsala University\nMuch of the compl
 exity and overhead (directory\, state bits\, invalidations\, broadcasts) o
 f a typical hardware coherence implementation stems from the effort to mak
 e it “invisible” even to the strongest memory consistency models. In t
 his talk\, we show how a much simpler\, directory-less/broadcast-less\, mu
 lticore coherence can outperform a directory protocol without its complexi
 ty and overhead\, with just a data-race-free guarantee from software. This
  simplification of coherence brings further simplifications to the entire 
 on-chip memory system\, for example unconstrained scaling to multiple buse
 s\, simple on-chip networks\, and a new solution for efficient virtual-cac
 he coherence. Significant area\, energy\, and performance benefits ensue a
 s a result of simplifying the multicore memory organization\, making our a
 pproach a prime candidate for coherent\, shared-virtual-memory\, heterogen
 eous architectures.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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