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SUMMARY:High Density On-Chip Memories for Future Processors 
DTSTART:20110328T150000
DTSTAMP:20260507T084429Z
UID:70d54c17c753856459128d7dae30ffe775796fb645278b8be7936c70
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Kaushik ROY\, Electrical and Computer Engineering Facult
 y\, Purdue University\nScaling of technology has adverse effects on stabil
 ity of on-chip memories.\n\nDue to increased leakage current and parameter
  variations and the need for minimal sized transistors for high density\, 
 the standard 6T SRAM cells show high failure rate at low supply voltages. 
 In this talk I will explore different memory design options and technologi
 es for future on-chip caches. In particular\, I will focus on design and o
 ptimization of spin-transfer torque magnetic memories (using spin as a sta
 te variable) which has the possibility of replacing high level on-chip cac
 hes/main-memory in future processors. Finally (time permitting)\, I will c
 onsider the possibilities of logic design using spin as a state variable. 
LOCATION:ELA 2
STATUS:CONFIRMED
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