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SUMMARY:Die-Stacked DRAM Caches for Servers: Hit Ratio\, Latency\, or Band
 width? Have It All with Footprint Cache
DTSTART:20130620T140000
DTEND:20130620T150000
DTSTAMP:20260511T081308Z
UID:df4675b880607ba6fe5383b9ec8d3d155608bcad9c17f87b2a9e517f
CATEGORIES:Conferences - Seminars
DESCRIPTION:Djordje Jevdjic\, Parallel Systems Architecture\, EPFL\nAbstra
 ct:\nRecent research advocates using large die-stacked DRAM caches to brea
 k the memory bandwidth wall. Existing DRAM cache designs fall into one of 
 two categories — block-based and page-based. The former organize data in
  conventional blocks (e.g.\, 64B)\, ensuring low off-chip bandwidth utiliz
 ation\, but co-locate tags and data in the stacked DRAM\, incurring high l
 ookup latency. Furthermore\, such designs suffer from low hit ratios due t
 o poor\ntemporal locality. In contrast\, page-based caches\, which manage 
 data at larger granularity (e.g.\, 4KB pages)\, allow for reduced tag arra
 y overhead and fast lookup\, and leverage high spatial locality at the cos
 t of moving large amounts of data on and off the chip.\nThis work introduc
 es Footprint Cache\, an efficient die-stacked DRAM cache design for server
  processors. Footprint Cache allocates data at the granularity of pages\, 
 but identifies and fetches only those blocks within a page that will be to
 uched during the page's residency in the cache — i.e.\, the page's footp
 rint. In doing so\, Footprint Cache eliminates the excessive off-chip traf
 fic associated with page-based designs\, while preserving their high hit r
 atio\, small tag array overhead\, and low lookup latency. Cycle-accurate s
 imulation results of a 16-core server with up to 512MB Footprint Cache ind
 icate a 57% performance improvement over a baseline chip without a die-sta
 cked cache. Compared to a state-of-the-art block-based design\, our design
  improves performance by 13% while reducing dynamic energy of stacked DRAM
  by 24%.
LOCATION:BC 410 https://plan.epfl.ch/?room==BC%20410
STATUS:CONFIRMED
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