BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Memento EPFL//
BEGIN:VEVENT
SUMMARY:A Low-Overhead Asynchronous Interconnection Network for GALS Chip 
 Multiprocessors
DTSTART:20110321T111500
DTSTAMP:20260502T113629Z
UID:ebc2b0a94201c77818f16ee092ae64e4ff2fb6b8ccc1e8393bc35054
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Steven M. Nowick\, Columbia University\nThere has been a
  resurgence of interest in asynchronous (i.e. clockless) digital design in
  recent years\, as designers confront formidable challenges of high-speed 
 clock distribution\, chip complexity\, power\, design time\, mixed-timing 
 domains and reusability.\n\nThis talk is in two parts.  In the first part\
 , I will give a brief overview of asynchronous design\, including motivati
 on and highlights of recent industry activity (Intel\, Boeing\, Sun\, Phil
 ips) and academia. I will also briefly survey some of my active research a
 reas: (i) CAD tools for asynchronous circuits and systems\, (ii) mixed-tim
 ing interfaces\, and (iii) low-power delay-insensitive global communicatio
 n.\n\nIn the second part\, I present a new asynchronous interconnection ne
 twork for globally-asynchronous locally-synchronous (GALS) chip multiproce
 ssors. The network eliminates the need for global clock distribution\, and
  can interface multiple synchronous timing domains operating at unrelated 
 clock rates.  In particular\, two new highly-concurrent asynchronous compo
 nents are introduced which provide simple routing and arbitration/merge fu
 nctions.  Post-layout simulations indicate that comparable recent synchron
 ous router nodes\, based on a latency-insensitive design style\, have 5.6-
 10.7x more energy per packet and 2.8-6.4x greater area than the new asynch
 ronous nodes.  Pre-layout system-level network simulations\, using post-la
 yout nodes\, are then performed for the asynchronous network and a fabrica
 ted synchronous network (800 MHz\, 1.36 GHz) in identical commercial 90nm 
 technology.  Under random traffic\, the new network provides significantly
  lower latency and competitive throughput over the entire operating range 
 of the the 800 MHz network and through mid-range traffic rates for the 1.3
 6 GHz network\, but with degradation at higher traffic rates. Low end-to-e
 nd latencies\, through 6 router nodes and 5 hops\, of 5.2ns (at moderate l
 oad) were observed.\n\nSimulations are also presented for a GALS network\,
  running both \nrandom traffic and several parallel benchmark kernels\, th
 e latter co-simulated with a  shared-memory parallel CMP architecture\, as
  well as directions for further improvement.
LOCATION:ELA 2
STATUS:CONFIRMED
END:VEVENT
END:VCALENDAR