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SUMMARY:The Design and Implementation of a Database Processing Unit
DTSTART:20131205T140000
DTEND:20131205T153000
DTSTAMP:20260509T054219Z
UID:4910dafcc53acd172b79c98d835fcc5c415530ea3940cbcc0865eeda
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Martha Kim\, Columbia University\nBio: Martha Kim is an 
 Assistant Professor of Computer Science at Columbia University where she l
 eads the ARCADE Lab. Kim's research interests are in computer architecture
 \, parallel programming\, compilers\, and low-power computing. Her work ha
 s explored low-cost chip manufacturing systems\, reconfigurable communicat
 ion networks\, and fine-grained parallel application profiling techniques.
  Her current research focuses on hardware and software techniques to impro
 ve the usability of hardware accelerators as well as data-centric accelera
 tor design. Kim holds a PhD in Computer Science and Engineering from the U
 niversity of Washington and a bachelors in Computer Science from Harvard U
 niversity. She is the recipient of the 2013 Rodriguez Family Award in reco
 gnition of the research achievements of underrepresented junior faculty an
 d a 2013 NSF CAREER award. \nWith the global pool of data growing at 2.5 q
 uintillion bytes per day and 90% of it produced in the last two years\, th
 ere is no doubt the era of big data has arrived. This talk presents a targ
 eted deployment of hardware accelerators to improve the throughput and ene
 rgy efficiency of large-scale data processing. This talk describes Databas
 e Processing Units\, or DPUs\, a class domain-specific database processors
  that can efficiently handle database applications\, and present the instr
 uction set architecture\, microarchitecture\, and hardware implementation 
 of one DPU\, called the Q100.  The Q100 has a collection of heterogeneous
  ASIC tiles that process relational tables and columns quickly and energy-
 efficiently.  The architecture uses coarse grained instructions that mani
 pulate streams of data\, thereby maximizing pipeline and data parallelism\
 , and minimizing the need to time multiplex the accelerator tiles and spil
 l intermediate results to memory.  This talk will outline the motivation\
 , design\, evaluation and challenges of such data processing systems.
LOCATION:BC 410 https://plan.epfl.ch/?room==BC%20410
STATUS:CONFIRMED
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