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SUMMARY:2.5D and 3D IC --- The Status\, The Challenges\, and The Prospect
DTSTART:20140124T110000
DTEND:20140124T120000
DTSTAMP:20260924T105508Z
UID:c9166d932fe3893f9f8e0042b9fae6d31f7acb7ce664311489e84a89
CATEGORIES:Conferences - Seminars
DESCRIPTION:Hsien-Hsin Sean Lee\, TSMC and Georgia Tech\nAs device scaling
  faces several fundamental changes due to physical limitations\, tight int
 egration in the vertical dimension emerges to be the frontrunner technolog
 y to continue Gordon Moore’s prophecy. A broad definition of vertical in
 tegration includes novel wafer-level packaging schemes\, stacking multiple
  silicon dice on a passive silicon-interposer (2.5D)\, true 3D die-stacked
  IC\, and monolithic 3D fabrication. These highly anticipated solutions no
 t only pack more transistors on a given footprint to reduce the form facto
 r\, they also offer advantages such as immense memory bandwidth\, low powe
 r consumption\, fast interconnect\, flexibility in integration\, etc. In t
 his talk\, I will review and present my view\, from industry’s perspecti
 ve\, on the latest art in 2.5D and 3D integration\, their major challenges
  for market acceptance and productization\, and the (near-)future outlook.
  
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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