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VERSION:2.0
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SUMMARY:Galaxy: A High-Performance Energy-Efficient Multi-Chip Architectur
 e using Photonic Interconnects
DTSTART:20140424T140000
DTEND:20140424T153000
DTSTAMP:20260407T002652Z
UID:a29f63d4589e78b38a6e8c08d13c62f8ea627221c502648d804edd88
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Nikos Hardavellas\, Northwestern University\nThe scalabi
 lity trends of modern semiconductor technology lead to increasingly dense 
 multicore chips. Unfortunately\, physical limitations in area\, power\, of
 f-chip bandwidth\, and yield constrain single-chip designs to a relatively
  small number of cores\, beyond which scaling becomes impractical. Multi-c
 hip designs overcome these constraints\, and can reach scales impossible t
 o realize with conventional single-chip architectures. However\, to delive
 r commensurate performance\, multi-chip architectures require a cross-chip
  interconnect with bandwidth\, latency\, and energy consumption well beyon
 d the reach of electrical signaling.  In this talk I will describe Galaxy
 \, an architecture that enables the construction of a many-core “virtual
  macrochip” by connecting multiple smaller chiplets through optical fibe
 rs. The low optical loss of fibers allows the flexible placement of chiple
 ts\, and offers simpler packaging\, power\, and heat requirements. At the 
 same time\, the low latency and high bandwidth density of optical signalin
 g maintain the tight coupling of cores\, allowing the virtual chip to matc
 h the performance of a single chip that is not subject to area\, power\, a
 nd bandwidth limitations. Galaxy outperforms the best alternative by 2-4x 
 and attains 3-7x lower energy-delay product\, while it can scale beyond 4K
  cores. On top of this\, Ge-based on-chip lasers allow control mechanisms 
 to adapt the laser to the interconnect demands\, saving up to 77% of the l
 aser power.\nBio: Nikos Hardavellas is the June and Donald Brewer Assistan
 t Professor of Electrical Engineering and Computer Science at Northwestern
  University. His research interests include parallel computer architecture
 \, memory systems\, optical interconnects\, elastic fidelity computing\, a
 nd design for dark silicon. Prior to joining Northwestern University\, he 
 contributed to the design of several generations of Alpha processors and h
 igh-end multiprocessor servers at Digital Equipment Corp. (DEC)\, Compaq C
 omputer Corp.\, and Hewlett-Packard. He became a Searle Fellow in 2012\, a
 nd received an IEEE Micro Top Picks from Computer Architecture Conferences
  in 2010\, a Best Demonstration Award in ICDE 2006\, and a Technical Award
  for Contributions to the Alpha Microprocessor from Compaq Computer Corp. 
 in 2000. Nikos holds a Ph.D. in Computer Science from Carnegie Mellon Univ
 ersity. multiprocessor servers at Digital Equipment Corp. (DEC)\, Compaq C
 omputer Corp.\, and Hewlett-Packard. He became a Searle Fellow in 2012\, a
 nd received an IEEE Micro Top Picks from Computer Architecture Conferences
  in 2010\, a Best Demonstration Award in ICDE 2006\, and a Technical Award
  for Contributions to the Alpha Microprocessor from Compaq Computer Corp. 
 in 2000. Nikos holds a Ph.D. in Computer Science from Carnegie Mellon Univ
 ersity.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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