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SUMMARY:Spatial Computing and the Triggered Instruction Control Paradigm
DTSTART:20140605T110000
DTSTAMP:20260407T025748Z
UID:177ae584b8b05ac1253a02ffd9e8e02ba33dabac9d88a7f2358ed24d
CATEGORIES:Conferences - Seminars
DESCRIPTION:Joel EMER\, Intel in Hudson\nThe historical improvements in th
 e performance of general-purpose processors have long provided opportuniti
 es for application innovation. Word processing\, spreadsheets\, desktop pu
 blishing\, networking and various game genres are just some of the many ap
 plications that have arisen because of the increasing capabilities and the
  versatility of general-purpose processors. Key to these innovations is th
 e fact that general-purpose processors do not predefine the applications t
 hat they are going to run.\nCurrently\, the capabilities of individual gen
 eral-purpose processors are encountering challenges\, such as diminishing 
 returns in exploiting instruction-level parallelism and power limits. As a
  consequence\, a variety of approaches are being employed to address this 
 situation\, including adding myriad dedicated accelerators. Unfortunately\
 , while this improves performance it sacrifices generality. More specifica
 lly\, the time\, difficulty and cost of special purpose design preclude de
 dicated logic from serving as a viable avenue for application innovation.\
 nThere recently has been progress in addressing this dilemma between provi
 ding programmability and higher performance via an interesting middle grou
 nd between fully general-purpose computing and dedicated logic. In specifi
 c\, spatial computing\, where the computation is mapped spatially onto an 
 array of small programmable processing elements addresses many of the cost
 -related liabilities of dedicated logic and is increasingly being applied 
 to general computation problems. While field prgrammable gate arrays (FPGA
 s) are the best know spatial computing platform there are also a number of
  coarse grained variants.\nIn this talk\, we will examine the range of spa
 tial computing alternatives and explore in more depth the concept of trigg
 ered instructions\, a novel control paradigm for arrays of processing elem
 ents (PEs) aimed at exploiting spatial parallelism. Triggered instructions
  completely eliminate the program counter and allow programs to transition
  concisely between states without explicit branch instructions. They also 
 allow efficient reactivity to inter-PE communication traffic. The approach
  provides a unified mechanism to avoid over-serialized execution\, essenti
 ally achieving the effect of techniques such as dynamic instruction reorde
 ring and multithreading\, which each require distinct hardware mechanisms 
 in a traditional sequential architecture.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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