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SUMMARY:Carbon Nanotube Computer: Transforming Scientific Discoveries into
  Working Systems by Prof. Subhasish Mitra\, Stanford University
DTSTART:20140718T100000
DTEND:20140718T120000
DTSTAMP:20260511T050415Z
UID:1b008bd16780e8ab3057b029f0a490c7942f9c47ed1a5d191a0438e7
CATEGORIES:Conferences - Seminars
DESCRIPTION:Professor Subhasish Mitra.\nProf. Subhasish Mitra directs the 
 Robust Systems Group in the Department of Electrical Engineering and the D
 epartment of Computer Science of Stanford University\, where he is the Cha
 mbers Faculty Scholar of Engineering. Prior to joining Stanford\, he was a
  Principal Engineer at Intel Corporation.   Prof. Mitra's research intere
 sts include robust system design\, VLSI design\, CAD\, validation and test
 \, and emerging nanotechnologies.  His X-Compact technique for test compr
 ession has been key to cost-effective manufacturing and high-quality testi
 ng of a vast majority of electronic systems\, including numerous Intel pro
 ducts. X-Compact and its derivatives have been implemented in widely-used 
 commercial Electronic Design Automation tools. His work on carbon nanotube
  imperfection-immune digital VLSI\, jointly with his students and collabor
 ators\, resulted in the demonstration of the first carbon nanotube compute
 r\, and it was featured on the cover of NATURE. The National Science Found
 ation presented this work as a Research Highlight to the US Congress\, and
  it also was highlighted as "an important\, scientific breakthrough" by th
 e BBC\, Economist\, EE Times\, IEEE Spectrum\, MIT Technology Review\, Nat
 ional Public Radio\, New York Times\, Scientific American\, Time\, Wall St
 reet Journal\, Washington Post\, and numerous other organizations worldwid
 e.   Prof. Mitra's honors include the Presidential Early Career Award for
  Scientists and Engineers from the White House\, ACM SIGDA/IEEE CEDA A. Ri
 chard Newton Technical Impact Award in Electronic Design Automation\, and 
 the Intel Achievement Award\, Intel’s highest corporate honor.  He and 
 his students published several award-winning papers at major venues: IEEE/
 ACM Design Automation Conference\, IEEE International Solid-State Circuits
  Conference\, IEEE International Test Conference\, IEEE Transactions on CA
 D\, IEEE VLSI Test Symposium\, Intel Design and Test Technology Conference
 \, and the Symposium on VLSI Technology. At Stanford\, he has been honored
  several times by graduating seniors "for being important to them during t
 heir time at Stanford."   Prof. Mitra has served on numerous conference c
 ommittees and journal editorial boards. He served on DARPA's Information S
 cience and Technology Board as an invited member. He is a Fellow of the IE
 EE. \nCarbon Nanotube Field Effect Transistors (CNFETs) are excellent cand
 idates for building highly energy-efficient future electronic systems. Unf
 ortunately\, carbon nanotubes (CNTs) are subject to substantial inherent i
 mperfections that pose major obstacles to the design of robust and very la
 rge-scale CNFET digital systems:   • It is nearly impossible to guarant
 ee perfect alignment and positioning of all CNTs. This limitation introduc
 es stray conducting paths\, resulting in incorrect circuit functionality. 
   • CNTs can be metallic or semiconducting depending on chirality. Meta
 llic CNTs result in excessive leakage and incorrect circuit functionality.
    A combination of design and processing techniques overcomes these chal
 lenges by creating robust CNFET digital systems that are immune to these i
 nherent imperfections. This imperfection-immune paradigm enables the first
  experimental demonstration of the carbon nanotube computer\, and\, more g
 enerally\, arbitrary digital systems that can be built using CNFETs. Monol
 ithically-integrated three-dimensional CNFET digital systems will also be 
 discussed.   This research was performed at Stanford University in collab
 oration with Prof. H.-S. Philip Wong and several graduate students.\nRefre
 shments will be served at 1:45pm in front of BC 410
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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