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SUMMARY:Challenges in Address Translation for Next-Generation Heterogeneou
 s Manycore Systems
DTSTART:20140918T110000
DTEND:20140918T120000
DTSTAMP:20260511T105538Z
UID:2fac052af88870ab2598381fa41a5db854f7c6e68fdfbdd7582a983e
CATEGORIES:Conferences - Seminars
DESCRIPTION:Abhishek Bhattacharjee\, Rutgers University\nAs systems run wo
 rkloads with ever-increasing memory footprints and incorporate large amoun
 ts of on-die heterogeneity\, maintaining programmer productivity and in ta
 ndem lowering memory access overheads becomes crucial. In particular\, the
  hardware and software stack of the virtual memory system becomes a critic
 al bottleneck because: (a) increasing memory footprints and larger last-le
 vel caches stress CPU Memory Management Units (TLBs\, MMU caches\, and pag
 e table walkers) aggressively\; and (b) on-chip accelerators require MMU s
 upport to support a programming model with unified address spaces\, at the
  risk of degraded performance.  In response\, this talk will focus on har
 dware/software techniques that leverage operating system page allocator pa
 tterns to increase TLB and MMU cache reach with modest hardware changes. W
 e will show that intelligently tracking OS allocation patterns allows for 
 exploiting "intermediate contiguity" between baseline page sizes and large
  pages. We will then design a first-cut MMU for GPUs\, the most mature acc
 eleration technology available today. The overall lessons from this work w
 ill show how to design next-generation MMUs for heterogeneous chips runnin
 g workloads with large\, multidimensional datasets.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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