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VERSION:2.0
PRODID:-//Memento EPFL//
BEGIN:VEVENT
SUMMARY:Memory Processing Units
DTSTART:20140919T140000
DTEND:20140919T151500
DTSTAMP:20260407T163512Z
UID:e317d48b729fc49de18a8ac79597978e3b936de51b7ede4abd00cd69
CATEGORIES:Conferences - Seminars
DESCRIPTION:Karu Sankaralingam\, University of Wisconsin-Madison\n3D die-s
 tacking of logic and DRAM warrants revisiting the ideas of near-memory pro
 cessing. We make the case for extending the current architectures with Mem
 ory Processing Units based on the commercially available HMC. On the progr
 amming model and execution side we propose memory remote-procedure calls t
 o offload entire pieces of computation to MPU. On the hardware side we arg
 ue that non-speculating\, low-frequency\, ultra-short pipeline processing 
 cores integrated closely with memory provide efficient processing. MPUs ar
 e applicable across a wide domain of workloads spanning data-intensive com
 puting\, networking\, and SQL database processing. Compared to a conventio
 nal multicore\, a system with MPUs using 128 ARM Cortex M3 micro-controlle
 rs per chip provides geometric mean 3.8X higher performance and 13X lower 
 energy.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CANCELLED
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