BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Memento EPFL//
BEGIN:VEVENT
SUMMARY:Pre-Synthesis Optimization of Arithmetic Circuits
DTSTART:20100910T163000
DTSTAMP:20260501T113319Z
UID:559d8fefde4d644b023d66e117394f4a4b8dadf50e7cc87c5ba1d476
CATEGORIES:Thesis defenses
DESCRIPTION:Monsieur Ajay Kumar Verma\nDirecteur de thèse : Prof. P. Ienn
 e\nInformatique
LOCATION:MXF 1 https://plan.epfl.ch/?room==MXF%201
STATUS:CONFIRMED
END:VEVENT
END:VCALENDAR