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VERSION:2.0
PRODID:-//Memento EPFL//
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SUMMARY:3D monolithic integration
DTSTART:20100624T160000
DTSTAMP:20260407T105548Z
UID:964393d9f95d57669f9d3dc9d14662bea9f6bc055c4d995614b81428
CATEGORIES:Conferences - Seminars
DESCRIPTION:Perrine Batude\, CEA-LETI\, Grenoble\, France \n Description 3
 D integration generates great interest to solve the fundamental limits of 
 scaling e.g. increasing delay in interconnections\, development costs and 
 variability. 3D monolithic integration\, by opposition to parallel (or bac
 k-end or TSV 3D integration) is the only technological option enabling to 
 fully benefit from the third dimension potential at the transistor scale t
 hanks to its high alignment precision (σMONO ~10nm compared to σTSV ~0.5
 µm ). The sequential processing of bottom and top FET is however challeng
 ing because of the potential detrimental impact on bottom FET of the top F
 ET processing. During this presentation\, an overview of Leti’s results 
 in that field will be given. 
LOCATION:INM 202
STATUS:CONFIRMED
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