BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Memento EPFL//
BEGIN:VEVENT
SUMMARY:Nanowires from 1D to 3D devices and memories
DTSTART:20100624T150000
DTSTAMP:20260506T020227Z
UID:abb99ec0b115d17b212f831ce16b5bfa986970e94b389fa3f3df33ae
CATEGORIES:Conferences - Seminars
DESCRIPTION:Thomas Ernst\, CEA-LETI\, Grenoble\, France\n3D CMOS nanowire 
 matrices and 2D thin film technologies recently developed\, enable not onl
 y sub-22nm CMOS device scaling\, but also ultimate co-integration of novel
  functionalities. For CMOS scaling\, Silicon-On-Insulator (SOI) or innovat
 ive Silicon-On-Nothing (SON) based 3D nanowires are proposed with common o
 r independent gates. Ultra-low static consumption\, as well as high drivin
 g current were achieved thanks to 3D stacked Gate-All-Around (GAA) nanowir
 e channels. The top-down nanowire techniques also open up new opportunitie
 s for hybridizing CMOS with novel functionalities such as 3D memories\, na
 no-oscillators and bio nano-sensors.
LOCATION:INM 202
STATUS:CONFIRMED
END:VEVENT
END:VCALENDAR