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SUMMARY:3D monolithic integration
DTSTART:20100624T160000
DTSTAMP:20260429T105042Z
UID:a5b95e13096b55cb8146014810065357c2244cdde2e34043e9041c80
CATEGORIES:Conferences - Seminars
DESCRIPTION:Perrine Batude\,  CEA-LETI\, Grenoble\, France\n3D integration
  generates great interest to solve the fundamental limits of scaling e.g. 
 increasing delay in interconnections\, development costs and variability. 
 3D monolithic integration\, by opposition to parallel (or back-end or TSV 
 3D integration) is the only technological option enabling to fully benefit
  from the third dimension potential at the transistor scale thanks to its 
 high alignment precision (σMONO ~10nm compared to σTSV ~0.5µm ). The se
 quential processing of bottom and top FET is however challenging because o
 f the potential detrimental impact on bottom FET of the top FET processing
 . During this presentation\, an overview of  Leti’s results in that fiel
 d will be given.
LOCATION:INM 202
STATUS:CONFIRMED
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