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SUMMARY:Nanowires from 1D to 3D devices and memories
DTSTART:20100624T150000
DTSTAMP:20260505T002748Z
UID:783087e6deee298ba816a7841368d5e6611e7286099367f704aaa7f4
CATEGORIES:Conferences - Seminars
DESCRIPTION:Thomas Ernst\,  CEA-LETI\, Grenoble\, France\n3D CMOS nanowire
  matrices and 2D thin film technologies recently developed\, enable not on
 ly sub-22nm CMOS device scaling\, but also ultimate co-integration of nove
 l functionalities. For CMOS scaling\, Silicon-On-Insulator (SOI) or innova
 tive Silicon-On-Nothing (SON) based 3D nanowires are proposed with common 
 or independent gates. Ultra-low static consumption\, as well as high drivi
 ng current were achieved thanks to 3D stacked Gate-All-Around (GAA) nanowi
 re channels. The top-down nanowire techniques also open up new opportuniti
 es for hybridizing CMOS with novel functionalities such as 3D memories\, n
 ano-oscillators and bio nano-sensors.
LOCATION:INM 202
STATUS:CONFIRMED
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