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SUMMARY:The Energy Challenges of Caching and Moving Data On Your Chip
DTSTART:20150319T161500
DTEND:20150319T173000
DTSTAMP:20260506T061803Z
UID:20ca3afbf1ae7c051da96a18ac5f300c8f6744083b1637c4a239d387
CATEGORIES:Conferences - Seminars
DESCRIPTION:Arrvindh Shriraman\, Assistant Professor in the School of Comp
 uting Sciences at Simon Fraser University\, Canada\nToday\, power constrai
 nts determine our ability to keep compute units active and busy. Interesti
 ngly\, storing and moving the data used and produced by the computation co
 nsumes more energy than the computation itself. Whether multicores\, GPUs 
 or fixed-function accelerators\, how we move and feed the computation unit
 s has critical impact on the programming model and the compute efficiency.
  We observe that unlike the latency overhead of the data movement which co
 uld potentially be hidden\, energy overhead dictates that we need to funda
 mentally reduce waste in the memory hierarchy.\nOur research focuses on ca
 che designs and coherence protocols that improve the energy efficiency of 
 the memory hierarchy by adapting the data storage and movement to the appl
 ication characteristics. I will particularly focus on the design of a new 
 coherence substrate\, Temporal Coherence\, that helps build energy efficie
 nt cache hierarchies for both GPUs and fixed-function accelerators. I will
  demonstrate how to realize release consistency on a GPU system at low ove
 rhead and discuss the improvements to the GPU programming model. I will al
 so demonstrate how temporal coherence can help offload fine-grain program 
 regions to fixed-function hardware accelerators and help move data efficie
 ntly between the accelerators. The overall lessons from our work will high
 light the importance of optimizing the memory hierarchy with a focus on en
 ergy efficiency.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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