BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Memento EPFL//
BEGIN:VEVENT
SUMMARY:From Variability-Tolerance to Approximate Computing
DTSTART:20150303T100000
DTSTAMP:20260407T002610Z
UID:f47a0af4d5f41605e3797544d1f1d665c1d2a7d95e8e34d396c2d607
CATEGORIES:Conferences - Seminars
DESCRIPTION:Abbas Rahimi\, UCSD\nBio: Abbas Rahimi is currently a fifth ye
 ar Ph.D. candidate in the Department of Computer Science and Engineering a
 t the University of California\, San Diego. He is working with Professor R
 ajesh Gupta and Professor Luca Benini. Since June 2010\, he has also been 
 with the Microelectronic Group at the University of Bologna. His research 
 interests are in the massively parallel integrated architectures\, approxi
 mate computing\, resilient system design\, design for robustness\, embedde
 d systems\, and on-chip interconnections. In these areas\, he has publishe
 d more than 20 papers in top tier conferences and journals. Mr. Rahimi rec
 eived the Best Paper Candidate at 50th IEEE/ACM Design Automation Conferen
 ce. He received the B.S. degree in computer engineering from the School of
  Electrical and Computer Engineering at the University of Tehran\, in Marc
 h 2010.\nVariation in performance and power across manufactured parts and 
 their operating conditions is an accepted reality in modern microelectroni
 c manufacturing processes with geometries in nanometer scales. These varia
 tions cause timing errors in computing systems that are typically avoided 
 by ultra-conservative multi-corner design margins. Keeping the focus on ti
 ming errors\, we investigated separate methodological approaches to predic
 t-and-prevent\, to detect-and-correct\, and finally\, to ignore timing err
 ors\; we evaluated their implications on cost\, performance and quality of
  the output results. Further\, we devise an arsenal of approximate computi
 ng and memoization-based optimizations techniques for improving cost and s
 cale of these approaches in massively parallel computing units\, such as t
 hose found in GP-GPUs and other clustered many-core accelerators. The resu
 lt was a framework for cross-layer (i.e.\, across software stack) and hybr
 id (i.e.\, across hardware and software) resiliency. This enabled us to co
 mbine error correction and error ignorance to devise a method for approxim
 ate error correction across the hardware/software interface via memoizatio
 n. That is\, ensuring safety of error-tolerance through a set of rules ver
 ified by a combination of design-time and runtime constraints. Together wi
 th the use of a memristive memory block\, spatial and temporal memoization
  was shown to significantly reduce the cost of resiliency and enhance the 
 range of variability-induced timing errors that can be recovered at very l
 ow cost.
LOCATION:MEB110 http://plan.epfl.ch/?lang=fr&room=MEB110
STATUS:CONFIRMED
END:VEVENT
END:VCALENDAR