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SUMMARY:From Variability-Tolerance to Approximate Computing
DTSTART:20150303T100000
DTEND:20150303T110000
DTSTAMP:20260407T114601Z
UID:532bc570f2cb14113a1563f659f74055590b673a5d7c695ddfc5f05f
CATEGORIES:Conferences - Seminars
DESCRIPTION:Dr. Abbas Rahimi\, Department of Computer Science and Engineer
 ing\, University of California\, San Diego\nAbbas Rahimi is currently a fi
 fth year Ph.D. candidate in the Department of Computer Science and Enginee
 ring at the University of California\, San Diego. He is working with Profe
 ssor Rajesh Gupta and Professor Luca Benini. Since June 2010\, he has also
  been with the Microelectronic Group at the University of Bologna. His res
 earch interests are in the massively parallel integrated architectures\, a
 pproximate computing\, resilient system design\, design for robustness\, e
 mbedded systems\, and on-chip interconnections. In these areas\, he has pu
 blished more than 20 papers in top tier conferences and journals. Mr. Rahi
 mi received the Best Paper Candidate at 50th IEEE/ACM Design Automation Co
 nference. He received the B.S. degree in computer engineering from the Sch
 ool of Electrical and Computer Engineering at the University of Tehran\, i
 n March 2010.\nVariation in performance and power across manufactured part
 s and their operating conditions is an accepted reality in modern microele
 ctronic manufacturing processes with geometries in nanometer scales. These
  variations cause timing errors in computing systems that are typically av
 oided by ultra-conservative multi-corner design margins. Keeping the focus
  on timing errors\, we investigated separate methodological approaches to 
 predict-and-prevent\, to detect-and-correct\, and finally\, to ignore timi
 ng errors\; we evaluated their implications on cost\, performance and qual
 ity of the output results. Further\, we devise an arsenal of approximate c
 omputing and memoization-based optimizations techniques for improving cost
  and scale of these approaches in massively parallel computing units\, suc
 h as those found in GP-GPUs and other clustered many-core accelerators. Th
 e result was a framework for cross-layer (i.e.\, across software stack) an
 d hybrid (i.e.\, across hardware and software) resiliency. This enabled us
  to combine error correction and error ignorance to devise a method for ap
 proximate error correction across the hardware/software interface via memo
 ization. That is\, ensuring safety of error-tolerance through a set of rul
 es verified by a combination of design-time and runtime constraints. Toget
 her with the use of a memristive memory block\, spatial and temporal memoi
 zation was shown to significantly reduce the cost of resiliency and enhanc
 e the range of variability-induced timing errors that can be recovered at 
 very low cost.
LOCATION:ME B1 10 http://plan.epfl.ch/?room=ME%20B1%20B10
STATUS:CONFIRMED
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