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SUMMARY:Exploiting Bandwidth in 3D-Integrated Chip Multiprocessors
DTSTART:20100625T123000
DTSTAMP:20260407T105856Z
UID:604132286ddbf18cb2c134384548b57300dc3a4b161cdf2522400a68
CATEGORIES:Conferences - Seminars
DESCRIPTION:Mr Ðorde Jevdic\nEDIC Candidacy Exam:Exam president: Prof. Gi
 ovanni De MicheliThesis director: Prof. Babak FalsafiCo-examiner: Prof. De
 jan KosticResearch Proposal 3D-Stacked Memory Architectures for Multi-core
  Processors  by G. H. Loh An Optimized 3D-Stacked Memory Architecture by E
 xploiting Excessive\, High-Density TSV Bandwidth. HPCA 2010  by Dong Hyuk 
 Woo\, Nak Hee Seong\, Dean L. Lewis\, and Hsien-Hsin S. Lee. Bridging the 
 Processor-Memory Performance Gap with 3D IC Technology. IEEE Design & Test
  of Computers\, 22(6):556.564\, 2005 by C. Liu\, I. Ganusov\, M. Burtscher
 \, and S. Tiwari
LOCATION:BC 329 https://plan.epfl.ch/?room==BC%20329
STATUS:CONFIRMED
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