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SUMMARY:D43D: 2nd Design for 3D Silicon Integration Workshop
DTSTART;VALUE=DATE:20100526
DTSTAMP:20260415T024239Z
UID:74392fb9fa670311c4724066f501aaa5059c0da8ee51d59351cc33c4
CATEGORIES:Conferences - Seminars
DESCRIPTION:Nano-Tera ED Project with Prof. David Atienza\n3-D ICs enable 
 dramatically improved performances at a much lower cost than new leading-e
 dge CMOS technology below 32 nm transistor fabrication. The success of the
 se new ICs depends on the availability of new methodologies and skills tha
 t are required to achieve acceptable design quality and productivity. This
  workshop brings together key actors from semiconductor companies\, system
  design houses and EDA industry to build a vision of the next step in 3D i
 ntegrated ICs design. Topics addressed are: Applications requiring 3D\, in
 terconnect architectures and thermal management for 3D ICs\, application p
 artitioning\, floor planning for 3D architectures\, modeling\, characteriz
 ation and testing for 3D ICs. 
LOCATION:INF328
STATUS:CONFIRMED
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