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SUMMARY:Interconnect and Memory Challenges in Interposer-based Systems 
DTSTART:20150624T103000
DTEND:20150624T113000
DTSTAMP:20260505T155152Z
UID:c95275b9994283fedea347121a8a1ab956733bf75762733e1d1c8619
CATEGORIES:Conferences - Seminars
DESCRIPTION:Gabriel Loh\, AMD Research\nSilicon interposers are already be
 ing considered for the aggressive integration of multiple 3D memory stacks
  in high-performance systems.  This provides significant amounts of memor
 y capacity within the package with very high bandwidths and low energy-per
 -bit costs.  However\, the full potential of all of this integrated memor
 y may be squandered if the in-package interconnect architecture cannot kee
 p up with the data rates provided by the multiple memory stacks.  In this
  talk\, I will first cover some of the key issues in providing the interco
 nnect support for aggressive interposer-based memory integration.  I will
  then present some recent research directions on how to leverage the resou
 rces of the interposer to attempt to ameliorate some of these issues\, and
  I will also explore promising directions for additional ways to use and e
 xploit interposers to further enhance such systems.  This leads to a disc
 ussion of open problems that can provide opportunities for new research co
 ntributions from the community.\nBio: Gabriel H. Loh is a Fellow Design En
 gineer in AMD Research\, the research and advanced development lab for Adv
 anced Micro Devices\, Inc.  Gabe received his Ph.D. and M.S. in computer 
 science from Yale University in 2002 and 1999\, respectively\, and his B.E
 ng. in electrical engineering from the Cooper Union in 1998.  Gabe was al
 so a tenured associate professor in the College of Computing at the Georgi
 a Institute of Technology\, a visiting researcher at Microsoft Research\, 
 and a senior researcher at Intel Corporation. His research interests inclu
 de computer architecture\, processor microarchitecture\, emerging technolo
 gies and 3D die stacking.  He is a senior member of IEEE and the ACM\, me
 mber of the MICRO “Hall of Fame”\, (co-)inventor on over forty US pate
 nt applications\, and a recipient of the US National Science Foundation Yo
 ung Faculty CAREER Award.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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