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SUMMARY:The Future of Nanoelectronics
DTSTART:20100308T161500
DTSTAMP:20260509T053938Z
UID:b312edb1605ef3b2518e38273e2f652cb446952df1f5792fb84e61e8
CATEGORIES:Conferences - Seminars
DESCRIPTION:Dr. Walter Riess\, IBM Research\, Switzerland\nScaling of semi
 conductor technology (CMOS) has been the driving force for the success of 
 information technology. However\, as device dimensions continue to shrink 
 into the nanometer length-scale regime\, conventional semiconductor techno
 logy will be approaching fundamental physical limits. New strategies\, inc
 luding the use of novel materials and 1D-device concepts\, innovative devi
 ce architectures\, and smart integration schemes need to be explored and a
 ssessed. They are crucial to extend current capabilities and maintain mome
 ntum beyond the end of the technology roadmap time frame (post-CMOS era.\n
 In this talk I will give a brief introduction into CMOS scaling\, I will p
 resent its limitations and show routes towards the ultimate switch includi
 ng the use of III-V materials and novel device concepts such as Impact ion
 ization MOSFETs and in particular the tunnel FET.    
LOCATION:CE 4\, Centre Est
STATUS:CONFIRMED
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