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VERSION:2.0
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SUMMARY:Breaking out of Control-Flow Jail: Single Assignment Compiler\, Si
 ngle-Assignment Architecture
DTSTART:20150716T133000
DTEND:20150716T143000
DTSTAMP:20261005T064920Z
UID:d059b0127ada0cc8f7f95ba8707d5f0bee2be2c1cf537f6cb17a4414
CATEGORIES:Conferences - Seminars
DESCRIPTION:Dr. Soner Onder\nShort Bio: Dr. Soner Onder is a professor at 
 the Department of Computer Science\, Michigan Technological University\nwh
 ere he leads the Computer Architecture Research Lab.  His research intere
 sts span Architecture\, Simulation and\nProgramming languages\, with an em
 phasis on program representations and compiler/architecture collaboration.
  He is the\ndesigner and implementor of one of the earliest architecture d
 escription languages\, ADL.  Dr. Soner Onder received his\nBS in Chemical
  Engineering in 1983\, his MS in Computer Engineering in 1988 from Middle 
 East Technical University\, Ankara\nand his PhD in Computer Science from t
 he University of Pittsburgh in 1999.  He started at Michigan Tech in 1999
 .  His\nresearch has been supported by National Science Foundation and DA
 RPA. Dr. Onder is a recipient of National Science\nFoundation's CAREER awa
 rd in 2004.\nDuring the past two decades\, micro-architecture research has
  primarily concentrated on exploiting program properties. We\nobserved tha
 t memory references of programs exhibit significant amount of temporal and
  spatial locality.  We exploit the\nlocality of references by using cache
  structures at the micro-architecture level. We realized that memory acces
 s\npatterns are predictable. We exploit this predictability by prefetching
  data to combat memory access latency. We noticed\nthat branch instruction
 s exhibit very predictable behavior and their behavior is correlated with 
 other branches.\nWe use these properties to design better branch predictor
 s.  Following years of success in understanding and\nexploiting these pro
 perties\, we have reached a plateau where obtaining significant gains by u
 tilizing program properties\nis no longer feasible.\nToday\, both the comp
 uting industry and academia have concentrated their efforts on thread-leve
 l and data-parallel\narchitectures\, citing the power constraints and the 
 end of Dennard scaling. While the number of transistors per chip\ncontinue
 d to increase until the age of dark-silicon\, these transistors have mostl
 y been utilized to build larger on-chip\nstorage as new micro-architecture
  techniques failed to demonstrate a commensurate increase in performance f
 or the added\ncomplexity. Therefore\, I argue that we have reached not onl
 y the end of Dennard scaling but also the limits of\nthe control flow para
 digm.\nIn this talk\, I will show that the middle layer of the series of a
 bstractions which extend from problems to\nmicro-architecture\, namely\, t
 he program representation\, is key to unleashing the performance potential
  of large hardware\nresources. I will present our work on a new program re
 presentation called Future Gated Single Assignment Form (FGSA)\nwhich repr
 esents programs in a partial-order that permits massive exploitation of in
 struction-level parallelism.\nMoreover\, FGSA can play a dual role as the 
 compiler's internal representation and the instruction set architecture of
 \nhardware. As a result\, it can be employed by compilers as a drop-in rep
 lacement for Static Single Assignment (SSA) form\nand it can be executed d
 irectly by control flow\, data flow\, or demand-driven architectures becau
 se it directly supports\nall three models.  FGSA can be derived from func
 tional\, imperative\, or demand-driven languages and thus also provides a\
 npath towards a unification of programming languages.\nI will conclude by 
 discussing our efforts to explore and develop demand-driven computing as a
  viable alternative to\ncontrol-flow computing. I will give an overview of
  a LaZy micro-architecture which can execute traditional code and\ndiscuss
  how massively parallel demand-driven architectures can be built based on 
 the FGSA representation.\nRefreshments will be available before the talk a
 s of 1:15pm.
LOCATION:BC 410 https://plan.epfl.ch/?room==BC%20410
STATUS:CONFIRMED
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