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SUMMARY:Optimizing communication architecture for many-core systems
DTSTART:20150917T160000
DTEND:20150917T170000
DTSTAMP:20260501T055936Z
UID:2bf0f7e2874e8e8ab6a70359fe036617feed074c7aa3ba731c71c0dc
CATEGORIES:Conferences - Seminars
DESCRIPTION:Jinho Lee\, ECE\, Seoul National University\, Korea\nNetwork-o
 n-chip and processing-in-memory\nAs more and more components tend to be in
 tegrated on a system\, the importance of optimizing interconnects has been
  continuously growing. In this talk\, I will introduce some optimization t
 echniques for the on-chip and off-chip interconnects.\nThe first part is a
 bout two routing algorithms for 3D stacked network-on-chips. The 3D stacki
 ng technology can provide many opportunities to designing computing system
 s. However\, most solutions for vertical communication\, such as TSVs and 
 inductive coupling suffer from the high cost and thus their numbers are of
 ten severely limited. I will investigate the design options for building 3
 D NoCs in such environment\, and propose routing algorithms for each optio
 n. \nThe second part  targets the off-chip link between processor and th
 e main memory. For years\, the memory wall problem has been limiting the s
 caling of many-core systems. To mitigate this\, the old “processing-in-m
 emory” paradigm is being revived to reduce the bandwidth requirements. I
  will present an approach to placing lightweight logic inside DRAM to gain
  significant speedups for a set of big-data kernels.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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