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SUMMARY:EPFL Workshop on Logic Synthesis and Verification
DTSTART:20151210T090000
DTEND:20151211T170000
DTSTAMP:20260407T042038Z
UID:2a8b9e6788d2de0b089dc0201ef269b99939f9a32afc38325ec88e19
CATEGORIES:Conferences - Seminars
DESCRIPTION:Nowadays\, EDA tools face challenges tougher than ever. On the
  one hand\, design sizes and goals in modern CMOS technology approach the 
 frontier of what is possibly achievable. On the other hand\, post-CMOS tec
 hnologies bring new computational paradigms for which standard EDA tools a
 re not suitable.\nNew research in fundamental EDA tasks\, such as synthesi
 s and verification\, is key to handle this situation.\nThe EPFL Workshop o
 n Logic Synthesis and Verification is a discussion forum on recent advance
 ments and future evolution of synthesis and verification techniques in EDA
 . It will take place at EPFL\, Lausanne\, Switzerland on December 10-11\, 
 2015. Top experts in the field will take part in the workshop to give pres
 entations on cutting edge themes and to participate in panel discussions.\
 nThe EPFL Workshop on Logic Synthesis and Verification is funded by nano-t
 era.ch to promote international scientific exchanges.\nRegisteration is re
 quired to attend and is free of charge. Please register on-line by clickin
 g here.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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