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SUMMARY:Design Optimizations for On-Chip Networks
DTSTART:20091020T151500
DTSTAMP:20260502T044030Z
UID:d471f8eec1e23bc6e793462493c1848645928368e86a9ed4913832bd
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Vijaykrishnan Narayanan\nAbstract:\nPerformance and powe
 r are the first order design metrics for Network-on-Chips (NoCs) that have
  become the de-facto standard in providing scalable communication backbone
 s for multicores/CMPs. In this talk\, I will present an overview of severa
 l design optimizations aimed at improving the performance and power effici
 ency of on-chip routers.\nFirst\, I will show the benefits of designing ro
 uters using 3D stacked technology. Second\, I will show the use of hybrid 
 topologies in enhancing the power and performance efficiencies in a NoC. F
 inally\, I introduce an approach that tunes the frequency of a router in r
 esponse to network load to manage both performance and power.\n\nShort CV:
 \nVijaykrishnan Narayanan is a Professor at the Computer Science and Engin
 eering department at The Pennsylvania State University with research inter
 ests in the areas of power-aware and reliable systems\, embedded systems\,
  reconfigurable architectures\, nano-architectures and computer architectu
 re. To learn more: Please visit http://www.cse.psu.edu/~vijay\n\nVijaykris
 hnan Narayanan's homepage
LOCATION:BC 410 https://plan.epfl.ch/?room==BC%20410
STATUS:CONFIRMED
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