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SUMMARY:Generating Hardware Accelerators from High-Level Programming Langu
 ages
DTSTART:20160701T133000
DTEND:20160701T153000
DTSTAMP:20260507T002337Z
UID:54bcf902411fa51b5461500ea14a903526239d4bf79eeeba29acdb02
CATEGORIES:Conferences - Seminars
DESCRIPTION:Lana Josipovic\nEDIC Candidacy Exam\nExam President: Prof. Gio
 vanni De Micheli\nThesis Director: Prof. Paolo Ienne\nCo-examiner: Prof. C
 hristos Kozyrakis\nBackground papersResource-Aware Throughput Optimization
  for High-Level\nSynthesisAutomatic Support for Multi-Module Parallelism\n
 from Computational PatternsRTL Synthesis: From Logic Synthesis to Automati
 c\nPipeliningAbstract\nDespite the numerous advantages of Field Programmab
 le Gate Arrays (FPGAs)\, their usage is still restricted to a narrow segme
 nt of developers: those with hardware design experience. At the same time\
 , high-level synthesis (HLS) is becoming increasingly popular as a way to 
 broaden the developer base. However\, HLS tools today suffer from numerous
  limitations and are not always able to deliver adequate design quality an
 d performance. There is an immediate requirement to explore the generation
  of efficient\, high-quality hardware accelerators from high-level program
 ming languages. This would instantly enable the widespread acceptance of F
 PGAs\, potentially leading to their adoption in many new market segments.
LOCATION:INF 113 http://plan.epfl.ch/?lang=en&room=INF+113
STATUS:CONFIRMED
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