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SUMMARY:Floating Point System Level Designs 
DTSTART:20090616T151500
DTSTAMP:20260407T131632Z
UID:2d3f1ef1d0d3cbe8eb8e46b32fb650418c1d3067ec42267574eaf8aa
CATEGORIES:Conferences - Seminars
DESCRIPTION:Mr Martin Langhammer\, Altera Corporation\nCurrent FPGA device
 s are optimized for fixed point applications\; the DSP precision\, logic t
 o DSP ratios\, and especially the routing density are all architected for 
 fixed point datapath requirements. Although small floating point datapaths
  can readily be implemented\, large systems with several hundred operators
  are impossible\, or result in severe performance degradation. A simple an
 alysis shows that the routing density needs to be doubled in order to supp
 ort IEEE754 floating point arithmetic\, but the increased device area woul
 d not be commercially feasible. In addition\, many algebraic and transcend
 ental functions have been traditionally implemented using CORDIC or other 
 bit-iterative methods\, which despite mapping well to FPGA logic structure
 s\, cause severe routing stress. Recently\, some new methods of floating p
 oint datapath construction\, such as fused floating point datapath synthes
 is\, have been proposed\, which result in large logic\, routing\, and late
 ncy reductions. Combined with newer function architectures\, which offer l
 inear cost and latency tradeoffs for traditionally non-linear complexity\,
  the construction of dense floating point systems with a very flexible ope
 rator mix is now possible. Design examples will be shown\, involving hundr
 eds of floating point operators\, with pushbutton timing closure to the sa
 me performance levels as fixed point designs. In particular\, matrix opera
 tion implementations such as matrix multiplication and Cholesky decomposit
 ion will be described\, along with the algorithmic changes required to opt
 imally use the wide\, but deeply pipelined\, vector operations that result
  from these new methods.
LOCATION:BC 01 https://plan.epfl.ch/?room==BC%2001
STATUS:CONFIRMED
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