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SUMMARY:Reliability of Wave Pipelining for NoC and FPGA
DTSTART:20090619T151500
DTSTAMP:20260922T015638Z
UID:747aa97a288b0ed1ae8d0812e48906d1e3ad325fa5de071748cb562d
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Guy Lemieux\, University of British Columbia\, Canada\nN
 etworks-on-Chip and FPGAs both require a programmable interconnect structu
 re where high-bandwidth\, low-latency communication is key to performance.
  Wave pipelining meets this requirement -- by sending data in waves throug
 h a logic network\, and carefully timing the release of new data\, maximum
  bandwidth and minimum latency can be achieved when everything is ideal. H
 owever\, the real world is never ideal. Noise sources and unpredictable ti
 ming variation leads to serious performance degradation of wave-pipelined 
 circuits. Accounting for noise\, we will show that traditional synchronous
  circuits with registers offer higher bandwidth and are more reliable than
  wave pipelining. However\, reliability and bandwidth can be improved by c
 ompensating for the main source of non-ideality\, accumulated timing jitte
 r\, through the use of surfing and distributed asynchronous FIFOs. To esti
 mate reliability of these circuits\, we have devised new techniques based 
 upon statistical timing. \nProf. Lemieux's homepage
LOCATION:BC 01 https://plan.epfl.ch/?room==BC%2001
STATUS:CONFIRMED
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