BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Memento EPFL// BEGIN:VEVENT SUMMARY:See in the Dark Low-light / Low-noise CMOS Image Sensors DTSTART:20161114T171500 DTSTAMP:20260506T231744Z UID:2557343d71a21208bf9c4d042da87aab58dfe2f4c7ffb93d810af808 CATEGORIES:Conferences - Seminars DESCRIPTION:Prof. Christian Enz\, EPFL\nThe continuous improvements of CMO S image sensors (CIS) in terms of quantum efficiency\, speed\, resolution\ , etc. enabled these low-cost devices to be used also in high-performance applications\, progressively replacing charge coupled devices (CCDs). Phot oelectron counting capability is the next step for CIS for ultimate low li ght performance and new imaging paradigms. With the recent improvements of the CIS sensitivity\, the sub-electron read noise limit has been reached. But this low noise level remains a bottleneck and further reduction towar ds deep sub-electron noise is required.\n\nIn this talk we will present so me recent results achieved in our lab in the field of low-noise CIS. We wi ll start with a review of fundamental noise mechanisms found in 4 transist ors (4T) pixels based on pinned photodiodes (PPD) and the associated reado ut chain circuits showing that the noise coming from the readout electroni cs is dominant. After a detailed noise analysis of the whole chain\, diffe rent noise reduction techniques are identified. Among these techniques\, i t is proposed to replace the traditional in-pixel thick oxide amplifying t ransistor with a thin oxide device for achieving minimum 1/f noise. This t echnique was evaluated in a first test chip designed in a 180 nm CIS proce ss and embedding optimized readout chains exploiting the new pixels togeth er with state-of-the-art 4T pixels optimized at process level for low 1/f noise. A mean input-referred noise of 0.4 erms was measured demonstrating a factor two reduction compared to the state-of-the-art pixels. A full VGA imager including a 4T pixel of 6.5 µm pitch with a properly sized and bi ased thin oxide PMOS source follower was then integrated in the same stand ard CIS process. The imager features an input-referred noise histogram fro m 0.25 e-rms to a few erms peaking at 0.48 erms at room temperature. This sub-0.5 erms noise performance is obtained with a full well capacity of 64 00 e and a frame rate that can go up to 80 fps. The VGA imager also featur es a fixed pattern noise as low as 0.77%\, a lag of 0.1% and a dark curren t of 5.6 e/s.\n\nThe integrated chip used a simple correlated double sampl ing (CDS) noise reduction technique. We will show that further noise reduc tion can be achieved thanks to correlated multiple sampling (CMS) using ve ry energy- and area-efficient passive switched-capacitor circuits. We will finish by looking at how CMOS technology scaling can help to further redu ce the input-referred noise\, potentially bringing it close to or even bel ow the photoelectron counting limit.\n\nBio: Christian Enz\, PhD\, Swiss F ederal Institute of Technology (EPFL)\, 1989. He is currently full Profess or at EPFL and Director of the Institute of Microengineering (IMT) and hea d of the IC Lab. He is also the manager of the EPFL site at Microcity in N euchâtel. Until April 2013 he was VP at the Swiss Center for Electronics and Microtechnology (CSEM) in Neuchâtel\, Switzerland where he was headin g the Integrated and Wireless Systems Division. Prior to joining the CSEM\ , he was Principal Senior Engineer at Conexant (formerly Rockwell Semicond uctor Systems)\, Newport Beach\, CA\, where he was responsible for the mod eling and characterization of MOS transistors for RF applications.\n\nFrom 1992 to 1997\, he was an Assistant Professor at EPFL\, working in the fie ld of low-power analog CMOS IC design and device modeling. In 1989 he was one of the founders of Smart Silicon Systems S.A. (S3)\, where he develope d several low-noise and low-power ICs\, mainly for high energy physics app lication at CERN. His technical interests and expertise are in the field o f ultralow-power analog and RF IC design\, wireless sensor networks and se miconductor device modeling. Together with E. Vittoz and F. Krummenacher h e is the developer of the EKV MOS transistor model and the author of the b ook "Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power an d RF IC Design" (Wiley\, 2006). He is the author and co-author of more tha n 250 scientific papers and has contributed to numerous conference present ations and advanced engineering courses.\n\nHe is an individual member of the Swiss Academy of Engineering Sciences (SATW). He has been member of se veral technical program committees\, including International Solid-State C ircuits Conference (ISSCC) and European Solid-State Circuits Conference (E SSCIRC). He is the General Co-chair of the ESSDERC-ESSCIRC conference that was held in Lausanne in September 2016. He has also served as a vice-chai r for the 2000 International Symposium on Low Power Electronics and Design (ISLPED)\, exhibit chair for the 2000 International Symposium on Circuits and Systems (ISCAS) and chair of the technical program committee for the 2006 European Solid-State Circuits Conference (ESSCIRC). He has been an el ected member of the IEEE Solid-State Circuits Society (SSCS) Administrativ e Commmittee (AdCom) from 2012 to 2014. He is also the Chair of the IEEE S olid-State Chapter of West Switzerland. LOCATION:SV 1717 https://plan.epfl.ch/?room==SV%201717 STATUS:CONFIRMED END:VEVENT END:VCALENDAR