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SUMMARY:ARMv8 : a next-generation vector architecture for HPC
DTSTART:20161130T103000
DTEND:20161130T113000
DTSTAMP:20260413T152851Z
UID:dcf09472840b76ccbc4ac2ef795fa2aaa77ce6891c4ba2fb8df839f5
CATEGORIES:Conferences - Seminars
DESCRIPTION:Grigorios Magklis\, ARM\nIn this talk we describe ARM's Scalab
 le Vector Extension that significantly extends the vector processing capab
 ilities associated with AArch64 (64-bit) execution in the ARM architecture
 \, now and into the future. Several goals guided the design of SVE. First\
 , the need to better address the compute requirements in domains such as h
 igh performance computing (HPC)\, data analytics and areas such as compute
 r vision and machine learning\, both now and into the future. Second\, a d
 esire for an architecture that scales across multiple implementations\, al
 lowing designers to choose the vector length most suitable for their power
 \, performance and area targets. Last\, a wish to minimize software develo
 pment costs as the vector length scales by improving the reach of compiler
  auto-vectorization technologies.
LOCATION:BC 420 https://plan.epfl.ch/?room==BC%20420
STATUS:CONFIRMED
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