BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Memento EPFL//
BEGIN:VEVENT
SUMMARY:Towards Accelerator-Rich Architectures and Systems
DTSTART:20170301T141500
DTSTAMP:20260413T103217Z
UID:b28b105d7e4c49541a2695235d51a6db6e9ad723b9c25790a550ac8b
CATEGORIES:Conferences - Seminars
DESCRIPTION:Dr Zhenman Fang\,  University of California Los Angeles\nAbstr
 act\nWith Intel’s $17.6B acquisition of Altera and the deployment of FPG
 As in major cloud service providers including Microsoft\, Amazon\, and IBM
 \, we are entering a new era of customized computing. In future architectu
 res and systems\, it is anticipated that there will be a sea of heterogene
 ous accelerators customized for important application domains\, such as ma
 chine learning and personalized healthcare\, to provide better performance
  and energy-efficiency. Many research problems are still open\, such as ho
 w to efficiently integrate accelerators into future chips\, how to efficie
 ntly deploy commodity accelerators in datacenters\, and how to program suc
 h accelerator-rich architectures and systems.\nIn this talk\, I will first
  briefly explain how customized accelerators can achieve orders-of-magnitu
 de performance improvement\, based on our open-source simulator PARADE [IC
 CAD 2015\, tutorials at ISCA 2015 & MICRO 2016]. Second\, I will present o
 ur initial work on CPU-accelerator co-design\, where we provide efficient 
 and unified address translation support between CPU cores and accelerators
  [HPCA 2017 Best Paper Nominee]. It shows that a simple two-level TLB desi
 gn for accelerators plus the host core MMU for accelerator page walking ca
 n be very efficient. On average\, it achieves 7.6x speedup over the naïve
  IOMMU and there is only 6.4% performance gap to the ideal address transla
 tion. Third\, I will present the open-source Blaze system that provides pr
 ogramming and runtime support to enable easy and efficient deployment of F
 PGA accelerators in datacenters [HotCloud 2016\, ACM SOCC 2016]. Blaze abs
 tracts accelerators-as-a-service (AaaS) and bridges the gap between big da
 ta applications such as Apache Spark programs and emerging accelerators su
 ch as FPGAs. By plugging a PCIe-based FPGA board into each CPU server\, it
  can improve the system throughput by several folds for a range of machine
  learning and computation genomics applications. Finally\, I will talk abo
 ut some future research areas that can enhance architecture\, programming\
 , compiler\, runtime\, and security support to accelerator-rich architectu
 res and systems.\n \nBio:\nDr. Zhenman Fang is a postdoc in the Computer 
 Science Department\, UCLA\, working with Prof. Jason Cong and Prof. Glenn 
 Reinman. He is a member of the NSF/Intel funded multi-university Center fo
 r Domain-Specific Computing (CDSC) and the SRC/DARPA funded multi-universi
 ty Center for Future Architectures Research (C-FAR). Zhenman received his 
 PhD in June 2014 from Fudan University\, China and spent the last 15 month
 s of his PhD program visiting University of Minnesota at Twin Cities. Zhen
 man's research lies at the boundary of heterogeneous and energy-efficient 
 accelerator-rich architectures\, big data workloads and systems\, and syst
 em-level design automation. He has published 10+ papers in top venues that
  span across computer architecture (HPCA\, TACO\, ICS)\, design automation
  (DAC\, ICCAD\, FCCM)\, and cloud computing (ACM SOCC). He received severa
 l awards\, including a postdoc fellowship from UCLA Institute of Digital R
 esearch and Education\, a best paper nominee of HPCA 2017\, a best demo aw
 ard (3rd place) at the C-FAR center annual review. More details can be fou
 nd in his personal website: https://sites.google.com/site/fangzhenman/ .\n
  
LOCATION:ME D2 1124 https://plan.epfl.ch/theme/generalite_thm_v2?request_l
 ocale=fr&room=me%20d2%201124&domain=places&dim_floor=2&lang=fr&dim_lang=fr
 &tree_groups=centres_nevralgiques%2Cacces%2Cmobilite_reduite%2Censeignem
STATUS:CONFIRMED
END:VEVENT
END:VCALENDAR