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SUMMARY:System Seminars : Exascale Computing: Challenges and Opportunities
DTSTART:20120220T130000
DTEND:20120220T143000
DTSTAMP:20260408T020406Z
UID:16ada1b300c675b8aef4d3d97ce0c03886dd0ce2dc67c4edbb4902f6
CATEGORIES:Conferences - Seminars
DESCRIPTION:Prof. Nader Bagherzadeh\, University of California - Irvine\, 
 USA (EECS Department)\nAbstract :\nThis talk gives an overview of current 
 efforts to develop the next generation HPC technologies in order to reach 
 the peak computing power that is more than 100 times faster than the fast
 est machine of 2011 from Japan. In order to meet this level of improvemen
 t\, many new hardware and software technologies must be developed to over
 come current technological barriers. One key area is to improve power eff
 iciency for the exascale architecture which is planned for 2020. The pow
 er efficiency requirements are not unlike what has been taking place for 
 embedded systems. Many architectural concepts from embedded systems may h
 ave to be revisited for HPS\, including heterogeneous computing and data 
 movement efficiency.\n\nBio :\nNader Bagherzadeh is a professor of compute
 r engineering in the department of electrical engineering and computer sc
 ience at the University of California\, Irvine\, where he served as a cha
 ir from 1998 to 2003. Dr Bagherzadeh has been involved in research and de
 velopment in the areas of:\ncomputer architecture\, reconfigurable computi
 ng\, VLSI chip design\, network-on-chip\, sensor networks\, and computer g
 raphics since he received a Ph.D. degree from the University of Texas at 
 Austin in 1987.\nProfessor Bagherzadeh has published more than 200 article
 s in peer-reviewed journals and conferences.  He has trained hundreds of
  students who have assumed key positions in software and computer systems
  design companies in the past twenty years.  He has been a PI or Co-PI o
 n more than 4 million dollars worth of research grants for developing nex
 t generation computer systems for applications in general purpose computi
 ng and digital signal processing.
LOCATION:INM 201 http://plan.epfl.ch/?lang=fr&room=INM201
STATUS:CONFIRMED
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