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SUMMARY:Fast Module-Based FPGA Compile Flow from High-Level Circuit Specif
 ications
DTSTART:20170614T163000
DTEND:20170614T180000
DTSTAMP:20260503T061807Z
UID:30e1a2b77abfaeb26fccb1cb55dc1d26b34b4d90ae40cf192e4c02f1
CATEGORIES:Conferences - Seminars
DESCRIPTION:Mikhail Asiatici\nEDIC candidacy exam\nExam president: Prof. G
 iovanni De Micheli\nThesis advisor: Prof. Paolo Ienne\nCo-examiner: Prof. 
 David Atienza Alonso\n\nAbstract\nTwo factors limit the mass adoption of F
 ield Programmable Gate Arrays (FPGAs) beyond the hardware developers commu
 nity: the non-traditional programming model\, and the low design productiv
 ity due to compile times in the order of hours.\nHigh-Level Synthesis (HLS
 ) represents a promising solution to the first problem as it automatically
  generates hardware designs from high-level programming languages familiar
  to software developers.\nTo tackle the second problem\, overlays and hard
  macros are two of the approaches that have been proposed.\nOverlays are v
 irtual programmable architectures implemented on the FPGA where applicatio
 ns can be mapped more easily than on the FPGA resources directly.\nHard ma
 cros are pre-processed modules that can be reused by the FPGA toolchain to
  quickly reimplement common functionalities.\nAlthough both approaches can
  reduce FPGA compile times by up to 4 orders of magnitude\, they impose im
 portant limitations on the structure of the designs they can handle and on
  the quality of the circuits they produce.\nIn this report\, we build up o
 n the results from the overlay and hard macro literature to propose new re
 search directions to achieve fast FPGA compilation of arbitrary designs\, 
 specified in high-level languages\, with minimal overheads.\n\nBackground 
 papers\nA high-performance overlay architecture for pipelined execution of
  data flow graphs. Field Programmable Logic and Applications (FPL)\,2013 2
 3rd International Conference on. IEEE\, 201\,  by Capalija\, Davor\, and
  Tarek S. Abdelrahman.\nFast\, Flexible High-Level Synthesis from OpenCL u
 sing Reconfiguration Contexts\, IEEE Micro 34.1 (2014): 42-53\, Coole J. a
 nd Grefg Stitt.\nDesign re-use for compile time reduction in FPGA high-lev
 el synthesis flows\, Field-Programmable Technology (FPT)\, 2014 Internatio
 nal Conference on. IEEE\, 2014 by Gort\, Marcel\, and Jason Anderson.\n\n
  
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STATUS:CONFIRMED
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