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SUMMARY:Specialized Processor Architecture for Datacentres
DTSTART:20170614T100000
DTEND:20170614T120000
DTSTAMP:20260407T183552Z
UID:9b5b1bc49ac824b592f7d0db93f4506d335efbd3cc9ad83a380bd4de
CATEGORIES:Conferences - Seminars
DESCRIPTION:Mark Sutherland\nEDIC candidacy exam\nExam president: Prof. Pa
 olo Ienne\nThesis advisor: Prof. Babak Falsafi\nCo-examiner: Prof. Giovann
 i de Micheli\n\nAbstract\nIn today's scale-out datacentres\, understanding
  the interactions of the high level system with the underlying microarchit
 ecture enables designers to extract more performance out of the hardware. 
 This candidacy proposal focuses on one of the outstanding issues in proces
 sor design: the instruction supply mechanism. We survey real profiling dat
 a from a production Google datacentre to motivate the study\, and show tha
 t today's processors take a suboptimal approach to both storing and prefet
 ching instructions. Then\, we cover two state-of the art instruction suppl
 y mechanisms presented in computer architecture literature\, both of which
  target this problem. Although both mechanisms present valuable insights\,
  we propose a new contribution\, to design a specialized processor that be
 tter matches the constraints of scale-out computing. Finally\, we present 
 a blueprint for a next-generation datacentre processor\, which shares its 
 instruction state between all of the component cores\, freeing up valuable
  die area and increasing overall performance density.\n\nBackground papers
 \nProfiling a Warehouse Scale Computer\, S. Kanev\, J. P. Darago\, K. Haz
 elwood\, P. Ranganathan\, T. Moseley\, G.-Y. Wei\, and D. Brooks.\nBoomera
 ng: a Metadata Free Architecture for Control Flow Delivery\, R. Kumar\, C
 .-C. Huang\, B. Grot\, and V. Nagarajan.\nSHIFT: Shared History Instructio
 n Fetch for Lean-core Server Processors\, C. Kaynak\, B. Grot\, and B. Fa
 lsafi. 
LOCATION:BC 329 https://plan.epfl.ch/?room==BC%20329
STATUS:CONFIRMED
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